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SN74ALVCH16823TIN/a64avai18-Bit Bus-Interface Flip-Flop With 3-State Outputs
SN74ALVCH16823DGGRTEXASN/a926avai18-Bit Bus-Interface Flip-Flop With 3-State Outputs
SN74ALVCH16823DLTIN/a250avai18-Bit Bus-Interface Flip-Flop With 3-State Outputs


SN74ALVCH16823DGGR ,18-Bit Bus-Interface Flip-Flop With 3-State OutputsSCES038F–JULY 1995–REVISED APRIL 2005FUNCTION TABLE(each 9-bit flip-flop)INPUTSOUTPUTQOE CLR CLKEN ..
SN74ALVCH16823DL ,18-Bit Bus-Interface Flip-Flop With 3-State OutputsFEATURESDGG OR DL PACKAGE• Member of the Texas Instruments Widebus™(TOP VIEW)Family1 561CLR 1CLK• E ..
SN74ALVCH16825DGGR ,18-Bit Buffer/Driver With 3-State OutputsFEATURESDGG OR DL PACKAGE• Member of the Texas Instruments Widebus™(TOP VIEW)Family1 561OE1 1OE2• E ..
SN74ALVCH16827 ,20-Bit Buffer/Driver With 3-State OutputsLOGIC DIAGRAM (POSITIVE LOGIC)1 281OE1 2OE156 291OE2 2OE255 2 42 151A1 1Y1 2A1 2Y1To Nine Other Cha ..
SN74ALVCH16827DGGR ,20-Bit Buffer/Driver With 3-State OutputsFEATURESDGG OR DL PACKAGE• Member of the Texas Instruments Widebus™(TOP VIEW)Family1OE1 1 56 1OE2• ..
SN74ALVCH16827DGGR ,20-Bit Buffer/Driver With 3-State OutputsMAXIMUM RATINGSover operating free-air temperature range (unless otherwise noted)MIN MAX UNITV Supp ..
SN74LVC2G00DCTR ,Dual 2-Input Positive-NAND GateMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV S ..
SN74LVC2G00DCUR ,Dual 2-Input Positive-NAND GateMaximum Ratings.. 411 Power Supply Recommendations... 117.2 ESD Ratings........ 412 Layout.... 127. ..
SN74LVC2G00DCURG4 , DUAL 2-INPUT POSITIVE-NAND GATE
SN74LVC2G00YEAR , DUAL 2 INPUT POSITIVE NAND GATE
SN74LVC2G00YZPR ,Dual 2-Input Positive-NAND GateBlock Diagram..... 93 Description....... 19.3 Feature Description...... 94 Simplified Schematic 19. ..
SN74LVC2G02DCTR ,Dual 2-Input Positive-NOR Gate SCES194M–APRIL 1999–REVISED NOVEMBER 2013(1)Recommended Operating ConditionsMIN MAX UNITOperating ..


SN74ALVCH16823-SN74ALVCH16823DGGR-SN74ALVCH16823DL
18-Bit Bus-Interface Flip-Flop With 3-State Outputs
FEATURES
DESCRIPTION
DGG OR DL PACKAGE
(TOP VIEW)

1CLR
1OE
1Q1
GND
1Q2
1Q3
VCC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2OE
2CLR
1CLK
1CLKEN
1D1
GND
1D2
1D3
VCC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2CLKEN
2CLK buffered output-enable (OE) input can be usedto place nine outputsin eithera normal logic state (highor
SN74ALVCH16823
18-BIT BUS-INTERFACE FLIP-FLOP
Memberof Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000V Per
MIL-STD-883, Method 3015; Exceeds 200V
Using Machine Model(C= 200 pF,R=0)
Latch-Up Exceeds 250 mA Per
JESD17
Bus Hold Data Inputs Eliminates the Need
for External Resistors
Package Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages

This 18-bit bus-interface flip-flop is designed for
1.65-Vto 3.6-V operation.
The SN74ALVCH16823 features 3-state outputs specifically for driving highly capacitiveor
relatively low-impedance loads. This device is
particularly suitable for implementing wider buffer
registers, I/O bidirectional bus drivers with
parity, and working registers.
The SN74ALVCH16823 can be used as two 9-bit
flip-flopsor one flip-flop. With the clock-enable
(CLKEN) input the D-type flip-flops enter dataon
the low-to-high transitions of the clock. Taking
CLKEN high the clock buffer, thus latching
the outputs. Taking the clear (CLR) input low causes
theQ outputs low independentlyof the clock.
low logic levels) the high-impedance state.In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capabilityto drive bus lines
without need foror pullup components.
The output-enable (OE) input does not affect the internalof the flip-flops. Old data can be retainedor
new data can entered while the outputs arein the high-impedance state. ensure the state during power upor power down, OE should be tiedto VCC througha pullup
resistor; the minimum valueof the resistoris determinedby current-sinking capabilityof the driver. bus-holdis providedto hold unusedor floating data inputsata valid logic level. for operation fromto 85°C.
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