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Home ›  SS58 > 74ALVCH16373DGGRG4-74ALVCH16373ZQLR-SN74ALVCH16373-SN74ALVCH16373DGGR-SN74ALVCH16373DL-SN74ALVCH16373DLR-SN74ALVCH16373KR,16-Bit Transparent D-Type Latch With 3-State Outputs
74ALVCH16373DGGRG4-74ALVCH16373ZQLR-SN74ALVCH16373-SN74ALVCH16373DGGR-SN74ALVCH16373DL Fast Delivery,Good Price
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Partno Mfg Dc Qty AvailableDescript
74ALVCH16373DGGRG4TIN/a450avai16-Bit Transparent D-Type Latch With 3-State Outputs 48-TSSOP -40 to 85
74ALVCH16373ZQLRTIN/a1000avai16-Bit Transparent D-Type Latch With 3-State Outputs
SN74ALVCH16373TIN/a63avai16-Bit Transparent D-Type Latch With 3-State Outputs
SN74ALVCH16373DGGRTIN/a6000avai16-Bit Transparent D-Type Latch With 3-State Outputs
SN74ALVCH16373DLTIN/a500avai16-Bit Transparent D-Type Latch With 3-State Outputs
SN74ALVCH16373DLRTIN/a457avai16-Bit Transparent D-Type Latch With 3-State Outputs
SN74ALVCH16373KRTEXASN/a1000avai16-Bit Transparent D-Type Latch With 3-State Outputs


SN74ALVCH16373DGGR ,16-Bit Transparent D-Type Latch With 3-State OutputsSCES020I–JULY 1995–REVISED NOVEMBER 2005ORDERING INFORMATION(1)T PACKAGE ORDERABLE PART NUMBER TOP- ..
SN74ALVCH16373DL ,16-Bit Transparent D-Type Latch With 3-State OutputsFEATURESDGG OR DL PACKAGE• Member of the Texas Instruments Widebus™(TOP VIEW)Family1 481OE 1LE• Ope ..
SN74ALVCH16373DLR ,16-Bit Transparent D-Type Latch With 3-State Outputs/sc/package.GQL OR ZQL PACKAGE (1)TERMINAL ASSIGNMENTS(TOP VIEW)(56-Ball GQL/ZQL Package)1 2 3 4 5 ..
SN74ALVCH16373KR ,16-Bit Transparent D-Type Latch With 3-State Outputsmaximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
SN74ALVCH16374 ,16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputsmaximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
SN74ALVCH16374DGGR ,16-Bit Edge-Triggered D-Type Flip-Flop With 3-State OutputsSN74ALVCH1637416-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPWITH 3-STATE OUTPUTS
SN74LVC245AN ,Octal Bus Transceiver With 3-State OutputsBlock Diagram..... 92 Applications..... 19.3 Feature Description...... 93 Description....... 19.4 D ..
SN74LVC245ANSR ,Octal Bus Transceiver With 3-State OutputsMaximum Ratings.. 412 Layout.... 117.2 ESD Ratings........ 412.1 Layout Guidelines.... 117.3 Recomm ..
SN74LVC245APW ,Octal Bus Transceiver With 3-State OutputsBlock Diagram..... 92 Applications..... 19.3 Feature Description...... 93 Description....... 19.4 D ..
SN74LVC245APW ,Octal Bus Transceiver With 3-State OutputsElectrical Characteristics....... 613.1 Trademarks..... 127.6 Switching Characteristics...... 613.2 ..
SN74LVC245APWLE ,Octal Bus Transceiver With 3-State OutputsMaximum Ratings.. 412 Layout.... 117.2 ESD Ratings........ 412.1 Layout Guidelines.... 117.3 Recomm ..
SN74LVC245APWR ,Octal Bus Transceiver With 3-State OutputsSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN74LVC245ASCAS218X– ..


74ALVCH16373DGGRG4-74ALVCH16373ZQLR-SN74ALVCH16373-SN74ALVCH16373DGGR-SN74ALVCH16373DL-SN74ALVCH16373DLR-SN74ALVCH16373KR
16-Bit Transparent D-Type Latch With 3-State Outputs 48-TSSOP -40 to 85
XXXX
DGG OR DL PACKAGE
(TOP VIEW)

1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE ensure high-impedance state during power up down, OE should be tiedto VCC througha pullup
SN74ALVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
Member the Texas Instruments Widebus™
Family
Operates From 1.65Vto 3.6V Max tpd 3.6 nsat 3.3V ±24-mA Driveat 3.3V Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD
ESD Protection Exceeds JESD22 2000-V Human-Body Model (A114-A) 200-V Model (A115-A)
DESCRIPTION/ORDERING INFORMATION

This 16-bit D-type latchis designed for
1.65-Vto 3.6-VVCC operation.
The SN74ALVCH16373is particularly suitable for
implementing buffer registers, I/O ports, bidirectional
bus drivers, working registers. This device can used as two 8-bit latches or one 16-bit latch.
When the (LE) inputis high, theQ
outputs follow the data (D) inputs. When LEis taken
low, theQ are latchedat the levels setupat
theD inputs. buffered (OE) input can be usedto
place the eight outputsin eithera normal logic state
(highor low levels)or the high-impedance state. the high-impedance state, the outputs neither
load nor the buslines significantly. The
high-impedance state and the increased drive provide
the capabilityto drive bus lines without need for
interfaceor components. OE does not affect
internal operations of the latch. Old data can be
retained or data can be entered while the
outputs are the high-impedance state.
resistor; the valueof the resistoris determined the current-sinking capabilityof the driver.
Active bus-hold circuitry holds unusedor undriven inputsata valid logic state. Useof pullupor pulldown resistors the bus-hold circuitryis not recommended.
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