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SN74ALVCH16260TIN/a56avai12-Bit To 24-Bit Multiplexed D-Type Latch With 3-State Outputs
SN74ALVCH16260DGGRTIN/a1565avai12-Bit To 24-Bit Multiplexed D-Type Latch With 3-State Outputs


SN74ALVCH16260DGGR ,12-Bit To 24-Bit Multiplexed D-Type Latch With 3-State OutputsFEATURESDGG OR DL PACKAGE• Member of the Texas Instruments Widebus™(TOP VIEW)FamilyOEA OE2B1 56• EP ..
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SN74ALVCH16260-SN74ALVCH16260DGGR
12-Bit To 24-Bit Multiplexed D-Type Latch With 3-State Outputs
FEATURES
DESCRIPTION
DGG OR DL PACKAGE
(TOP VIEW)

OEA
LE1B
2B3
GND
2B2
2B1
VCC
GND
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
LE2B
SEL
OE2B
LEA2B
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
LEA1B
OE1B
Address and/or data information canbe stored using the storage latches. The latch-enable (LE1B, LE2B,
SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
Member the Texas Instruments Widebus™
Family
EPIC™ Implanted
CMOS) Process
ESD Protection Exceeds 2000V Per
MIL-STD-883, Method 3015; Exceeds 200V
Using Machine Model(C= 200 pF,R=0)
Latch-Up Exceeds 250 mA Per
JESD17
Bus Hold Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages

This 12-bit 24-bit multiplexed D-type latch is
designed forto 3.6-V VCC operation.
The SN74ALVCH16260is used in applicationsin
which two separate data paths must be multiplexed
onto, or demultiplexed from,a single data path.
Typical applications include multiplexing and/or
demultiplexing address and data information in
microprocessor or bus-interface applications. This
device also is useful in memory-interleaving
applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and
2B1-2B12) available for address and/or data
transfer. The (OE1B, OE2B, and OEA)
inputs control the bus transceiver functions. The
OE1B and control signals also allow bank
controlin the direction.
LEA1B, and inputs are usedto control data storage. When the latch-enable inputis high, the latchis
transparent. the latch-enable input goes low, the presentat the inputsis latched and remains latched
until the latch-enable inputis returned high. ensure the state during power upor down, OE should be tiedto VCC througha pullup
resistor; the valueof the resistoris determined the current-sinking capabilityof the driver.
Active bus-hold circuitryis providedto hold unusedor floating data inputsata valid logic level.is characterized for operation from -40°Cto 85°C.
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