SN74ALVC164245DGGR ,16-Bit 2.5-V to 3.3-V/3.3-V To 5-V Level Shifting Transceiver With 3-State OutputsSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN74ALVC164245SCAS41 ..
SN74ALVC164245DL ,16-Bit 2.5-V to 3.3-V/3.3-V To 5-V Level Shifting Transceiver With 3-State OutputsFeatures... 18 Detailed Description........ 162 Applications..... 18.1 Overview.. 163 Description.. ..
SN74ALVC164245DLR ,16-Bit 2.5-V to 3.3-V/3.3-V To 5-V Level Shifting Transceiver With 3-State OutputsBlock Diagram... 164 Revision History........ 28.3 Feature Description.... 165 Pin Configuration an ..
SN74ALVC16835 ,18-Bit Universal Bus Driver With 3-State OutputsSCES125J–FEBRUARY 1998–REVISED NOVEMBER 2004GQL OR ZQL PACKAGE(TOP VIEW)1 2 3 4 5 6ABCDEFGHJK(1)TER ..
SN74ALVC16835DGGR ,18-Bit Universal Bus Driver With 3-State Outputsmaximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
SN74ALVC16835DGVR , 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SN74LVC1G79DCKR ,Single Positive-Edge-Triggered D-Type Flip-FlopBlock Diagram... 113 Description....... 18.3 Feature Description.... 114 Revision History........ 2 ..
SN74LVC1G79DCKRG4 ,Single Positive-Edge-Triggered D-Type Flip-Flop 5-SC70 -40 to 125Maximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV S ..
SN74LVC1G79DCKT ,Single Positive-Edge-Triggered D-Type Flip-FlopElectrical Characteristics....... 611.2 Layout Example....... 146.6 Timing Requirements: T = –40°C ..
SN74LVC1G79YZPR ,Single Positive-Edge-Triggered D-Type Flip-FlopLogic Diagram (Positive Logic)2CCLK CC4TGQC C CC1D TG TG TGC C CCopyright 2017, Texas Instruments ..
SN74LVC1G80DBVR ,Single Positive-Edge-Triggered D-Type Flip-FlopFeatures 3 DescriptionThis single positive-edge-triggered D-type flip-flop is1• Available in the Te ..
SN74LVC1G80DCKR ,Single Positive-Edge-Triggered D-Type Flip-FlopElectrical Characteristics....... 511.2 Layout Example....... 146.6 Timing Requirements: T = –40°C ..
74ALVC164245DGGRE4-74ALVC164245DGGRG4-74ALVC164245DLRG4-SN74ALVC164245-SN74ALVC164245DGGR-SN74ALVC164245DL-SN74ALVC164245DLR
16-Bit 2.5-V to 3.3-V/3.3-V To 5-V Level Shifting Transceiver With 3-State Outputs 48-TSSOP -40 to 85
1OE
2DIR
2A1
2OE Control Inputs VIH/VIL Levels Are Referencedto
VCCA Voltage Latch-Up Performance Exceeds 250 mA Per
JESD17
Applications Electronic Pointsof Sale Printers and Other Peripherals Motor Drives Wireless and Telecom Infrastructures Wearable Health and Fitness Devices
environment, and vice versa,or froma 3.3-Vtoa 5-V
environment, and vice versa.
The SN74ALVC164245is designed for asynchronous
communication between data buses. The control
circuitry (1DIR, 2DIR, 1OE, and 2OE)is poweredby
VCCA. ensure the high-impedance state during power up power down, the output-enable (OE) input should tiedto VCC througha pullup resistor; the minimum
valueof the resistoris determined by the current-
sinking capabilityof the driver.
The logic levelsof the direction-control (DIR) input
and the output-enable (OE) input activate either the
B-port outputs or the A-port outputs or place both
output ports into the high-impedance mode. The
device transmits data from theA busto theB bus
when the B-port outputs are activated, and from theB
bus to theA bus when the A-port outputs are
activated. The input circuitry on bothA andB ports
alwaysis active and must havea logic HIGHor LOW
level appliedto prevent excess ICC and ICCZ.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Logic Diagram (Positive Logic)
