SN74ALS996DW ,Octal D-Type Edge-Triggered Read-Back Latches SDAS098B − OCTOBER 1984 − REVISED JA ..
SN74ALS996DWR ,Octal D-Type Edge-Triggered Read-Back Latchesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN74ALVC00 ,Quadruple 2-Input Positive-NAND GateELECTRICAL CHARACTERISTICSover recommended operating free-air temperature range (unless otherwise n ..
SN74ALVC00D ,Quadruple 2-Input Positive-NAND GateMAXIMUM RATINGSover operating free-air temperature range (unless otherwise noted)MIN MAX UNITV Supp ..
SN74ALVC00DR ,Quadruple 2-Input Positive-NAND GateFEATURES • ESD Protection Exceeds JESD 22• Operates From 1.65 V to 3.6 V – 2000-V Human-Body Model ..
SN74ALVC00NSR ,Quadruple 2-Input Positive-NAND Gatemaximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
SN74LVC1G3157YZPR ,Single-Pole, Double-Throw Analog SwitchFeatures 3 DescriptionThis single channel single-pole double-throw (SPDT)1• ESD Protection Exceeds ..
SN74LVC1G3208DBVR ,Single 3-Input Positive OR-AND GateFEATURES DESCRIPTIONThis device is designed for 1.65-V to 5.5-V VCC2• Available in the Texas Instru ..
SN74LVC1G32DBVR ,Single 2-Input Positive-OR GateTable of Contents8.1 Overview.. 111
SN74LVC1G32DBVRG4 ,Single 2-Input Positive-OR Gate 5-SOT-23 -40 to 125Features 3 Description2This single 2-input positive-OR gate is designed for1• Available in the Ultr ..
SN74LVC1G32DBVT ,Single 2-Input Positive-OR GateFeatures, Description, and Device Information table..... 1• Added Pin Functions table. .... 4• Adde ..
SN74LVC1G32DBVTG4 ,Single 2-Input Positive-OR Gate 5-SOT-23 -40 to 125Block Diagram... 112 Applications..... 18.3 Feature Description.... 113 Description....... 18.4 Dev ..
SN74ALS996DW-SN74ALS996DWR
Octal D-Type Edge-Triggered Read-Back Latches
Package Options Include PlasticSmall-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
descriptionThese 8-bit latches are designed specifically for
storing the contents of the input data bus and
providing the capability of reading back the stored
data onto the input data bus. The Q outputs are
designed with bus-driving capability.
The edge-triggered flip-flops enter the data on the
low-to-high transition of the clock (CLK) input
when the enable (EN) input is low. Data can be
read back onto the data inputs by taking the read
(RD) input low, in addition to having EN low. When
EN is high, both the read-back and write modes
are disabled. Transitions on EN should only be
made with CLK high to prevent false clocking.
The polarity of the Q outputs can be controlled by
the polarity (T/C) input. When T/C is high, Q is the
same as is stored in the flip-flops. When T/C is low,
the output data is inverted. The Q outputs can be
placed in the high-impedance state by taking the
output-enable (OE) input high. OE does not affect
the internal operation of the register. Old data can
be retained or new data can be entered while the
outputs are off.
A low level at the clear (CLR) input resets the
internal registers low. The clear function is
asynchronous and overrides all other register
functions.
The -1 version of the SN74ALS996 is identical to the standard version, except that the recommended maximumOL for the -1 version is increased to 48 mA. There is no -1 version of the SN54ALS996.
The SN54ALS996 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74ALS996 is characterized for operation from 0°C to 70°C.
