SN74ALS563BDW ,Octal D-Type Transparent Latches With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ALS563BN ,Octal D-Type Transparent Latches With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN74ALS563BN ,Octal D-Type Transparent Latches With 3-State Outputs SDAS163B − DECEMBER 1982 − ..
SN74ALS564B ,Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs SN54ALS564B, SN74ALS564B OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS164B – AP ..
SN74ALS564BDW ,Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN74ALS564BN ,Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputslogic diagram (positive logic)11OE ENOE11CLK C111CLK2 191D 1D 1Q3 18C12D2Q 191Q4 1721D3D 1D3Q5 164D ..
SN74LVC16244AZQLR ,16-Bit Buffer/Driver With 3-State OutputsElectrical Characteristics—DC Limit Changes 813 Device and Documentation Support........ 147.6 Swi ..
SN74LVC16245 ,16-Bit Bus Transceiver With 3-State Outputs 48-SSOP -40 to 85
SN74LVC16245A ,16-Bit Bus Transceiver With 3-State OutputsSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN74LVC16245ASCES062 ..
SN74LVC16245ADGGR ,16-Bit Bus Transceiver With 3-State OutputsTable of Contents1
SN74LVC16245ADGVR ,16-Bit Bus Transceiver With 3-State OutputsFeatures 2 Applications1• Member of the Texas Instruments • Electronic Points of SaleWidebus™ Famil ..
SN74LVC16245ADL ,16-Bit Bus Transceiver With 3-State OutputsFeatures... 1 9 Detailed Description........ 119.1 Overview.. 112 Applications..... 19.2 Functional
SN74ALS563BDW-SN74ALS563BN
Octal D-Type Transparent Latches With 3-State Outputs
These 8-bit D-type transparent latches feature
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q
outputs follow the complements of data (D) inputs.
When LE is taken low, the outputs are latched at
the inverse of the levels set up at the D inputs.
A buffered output-enable (OE) input places the
eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and increased high logic
level provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the
latches. Old data can be retained or new data can
be entered while the outputs are in the
high-impedance state.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
at www.ti.com/sc/package.
