SN74ALS29833DW ,8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SN74ALS29833DWR , 8-BIT TO 9-BIT PARITY TRANSCEIVERS
SN74ALS29833NT ,8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SN74ALS29841NT ,10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74ALS299 ,8-Bit Universal Shift/Storage Registers With 3-State Outputs SN54ALS299, SN74ALS299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS SDAS220B – DEC ..
SN74ALS299DW ,8-Bit Universal Shift/Storage Registers With 3-State Outputs SN54ALS299, SN74ALS299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS SDAS220B – DEC ..
SN74LVC112ADBR ,Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And PresetFeatures 2 Applications1• Operates From 1.65 V to 3.6 V • Servers• Inputs Accept Voltages to 5.5 V ..
SN74LVC112ADGVR ,Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset SCAS289M–JANUARY 1993–REVISED DECEMBER 20146 Pin Configuration and FunctionsD,DB,DGV,NS,ORPWPACKAG ..
SN74LVC112ADGVRG4 ,Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-TVSOP -40 to 125Electrical Characteristics ...... 612.2 Layout Example....... 127.6 Timing Requirements, –40°C to 8 ..
SN74LVC112ADR ,Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And PresetMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV S ..
SN74LVC112ANSR ,Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And PresetBlock Diagram..... 94 Simplified Schematic 19.3 Feature Description...... 95 Revision History...... ..
SN74LVC112APW ,Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And PresetMaximum Ratings . 410.2 Typical Application .. 107.2 ESD Ratings........ 411 Power Supply Recommend ..
SN74ALS29833DW-SN74ALS29833DWR-SN74ALS29833NT
8-BIT TO 9-BIT PARITY TRANSCEIVERS
