SN74ALS273DWR ,Octal D-Type Positive-Edge-Triggered Flip-Flops With Clearlogic diagram (positive logic)1D 2D 3D 4D 5D 6D 7D 8D3 4 7 8 13 14 17 1811CLK1D 1D 1D 1D 1D 1D 1D 1 ..
SN74ALS273N ,Octal D-Type Positive-Edge-Triggered Flip-Flops With Clearmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ALS273NSR ,Octal D-Type Positive-Edge-Triggered Flip-Flops With Clearmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN74ALS27A ,Triple 3-Input Positive NOR Gatesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN74ALS27AD ,Triple 3-Input Positive NOR Gateselectrical characteristics over recommended operating free-air temperature range (unlessotherwise n ..
SN74ALS27ADR ,Triple 3-Input Positive NOR Gatesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN74LVC08ADRG4 ,Quadruple 2-Input Positive-AND Gate 14-SOIC -40 to 125Maximum Ratings . 511 Power Supply Recommendations... 127.2 ESD Ratings........ 512 Layout.... 127. ..
SN74LVC08ADTG4 , QUADRUPLE 2-INPUT POSITIVE-AND GATES
SN74LVC08ANSR ,Quadruple 2-Input Positive-AND GateLogic Diagram, Each Gate(Positive Logic)AYB1An IMPORTANT NOTICE at the end of this data sheet addre ..
SN74LVC08ANSRG4 , QUADRUPLE 2-INPUT POSITIVE-AND GATES
SN74LVC08APW ,Quadruple 2-Input Positive-AND GateLogic Diagram, Each Gate(Positive Logic)AYB1An IMPORTANT NOTICE at the end of this data sheet addre ..
SN74LVC08APWLE ,Quadruple 2-Input Positive-AND GateBlock Diagram... 103 Description....... 19.3 Feature Description.... 104 Revision History........ 2 ..
SN74ALS273-SN74ALS273DW-SN74ALS273DWR-SN74ALS273N-SN74ALS273NSR
Octal D-Type Positive-Edge-Triggered Flip-Flops With Clear
Applications Include:Buffer/Storage Registers
Shift Registers
Pattern Generators Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
descriptionThese octal positive-edge-triggered flip-flops
utilize TTL circuitry to implement D-type flip-flop
logic with a direct-clear (CLR) input.
Information at the data (D) inputs meeting the
setup-time requirements is transferred to the
Q outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a particular
voltage level and is not directly related to the
transition time of the positive-going pulse. When
CLK is at either the high or low level, the D input
signal has no effect at the output.
The SN54ALS273 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74ALS273 is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)GND
CLK1QCLR5D
GND
CLK
SN54ALS273... FK PACKAGE
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