SN74ALS191A ,4-Bit Synchronous Up/Down Binary Counters SDAS210C − DECEMBER 1982 − REVISED J ..
SN74ALS191ADR ,4-Bit Synchronous Up/Down Binary Counters SDAS210C − DECEMBER 1982 − REVISED J ..
SN74ALS191AN ,4-Bit Synchronous Up/Down Binary Counters SDAS210C − DECEMBER 1982 − REVISED J ..
SN74ALS191AN ,4-Bit Synchronous Up/Down Binary Counters SDAS210C − DECEMBER 1982 − REVISED J ..
SN74ALS193AN ,4-Bit Synchronous Up/Down Binary Counters With Dual Clock and Clear SDAS211C − DECE ..
SN74ALS20A ,Dual 4-Input Positive-NAND Gateslogic diagram (positive logic)11&1A 1A221B1B6641Y1Y 41C1C551D1D92A92A102B 81012 2Y 2B82C 2Y122C132D ..
SN74LV573APWR ,Octal Transparent D-Type Latches With 3-State OutputsSN54LV573A, SN74LV573AOCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCLS411I − APRIL 1998 − R ..
SN74LV573APWRG4 ,Octal Transparent D-Type Latches With 3-State Outputs 20-TSSOP -40 to 85maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LV573ARGYR ,Octal Transparent D-Type Latches With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage r ..
SN74LV574A ,Octal Edge-Triggered D-Type Flip-Flops With 3-State OutputsSN54LV574A, SN74LV574AOCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH 3-STATE OUTPUTSSCLS412I − APRIL 19 ..
SN74LV574ADBR ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LV574ADGVR ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputslogic diagram (positive logic)1OE11CLKC1191Q21D 1DTo Seven Other ChannelsPin numbers shown are for ..
SN74ALS191A-SN74ALS191ADR-SN74ALS191AN
4-Bit Synchronous Up/Down Binary Counters
Asynchronously Presettable With LoadControl Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
descriptionThe ’ALS191A are synchronous 4-bit reversible
up/down binary counters. Synchronous counting
operation is provided by having all flip-flops
clocked simultaneously so that the outputs
change coincidentally with each other when
instructed by the steering logic. This mode of
operation eliminates the output counting spikes
normally associated with asynchronous
(ripple-clock) counters.
The outputs of the four flip-flops are triggered on
a low-to-high-level transition of the clock (CLK)
input if the count enable (CTEN) input is low. A
high at CTEN inhibits counting. The direction of
the count is determined by the level of the
down/up (D/U) input. When D/U is low, the counter
counts up, and when D/U is high, the counter
counts down.
These counters feature a fully independent clock circuit. Changes at the control inputs (CTEN and D/U) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter is dictated solely by the conditions meeting the stable setup and hold times.
These counters are fully programmable. Each output can be preset to either level by placing a low on the LOAD
input and entering the desired data at the data inputs. The output changes to agree with the data inputs
independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers
by simply modifying the count length with the preset inputs.
CLK, D/U, and LOAD are buffered to lower the drive requirement, which significantly reduces the loading on
(current required by) clock drivers, for long parallel words.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
