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SN74ALS164A-SN74ALS164AD-SN74ALS164ADR-SN74ALS164AN-SN74ALS164ANSR Fast Delivery,Good Price
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SN74ALS164ATIN/a150avai8-Bit Parallel-Out Serial Shift Registers
SN74ALS164ADTIN/a153avai8-Bit Parallel-Out Serial Shift Registers
SN74ALS164ADRTIN/a2500avai8-Bit Parallel-Out Serial Shift Registers
SN74ALS164ANN/a47avai8-Bit Parallel-Out Serial Shift Registers
SN74ALS164ANSRTIN/a6626avai8-Bit Parallel-Out Serial Shift Registers


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SN74ALS164A-SN74ALS164AD-SN74ALS164ADR-SN74ALS164AN-SN74ALS164ANSR
8-Bit Parallel-Out Serial Shift Registers
Small-Outline (D) Packages and Standard
Plastic (N) 300-mil DIPs

description

This 8-bit parallel-out serial shift register features
AND-gated serial (A and B) inputs and an
asynchronous clear (CLR) input. The gated serial
inputs permit control over incoming data because a low at either input inhibits entry of the new data and resets
the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which
determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low,
provided that the minimum setup-time requirements are met. Clocking occurs on the low-to-high-level transition
of the clock (CLK) input. All inputs are diode clamped to minimize transmission-line effects.
The SN74ALS164A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
QA0, QB0, QH0 = the level of QA, QB, or QH, respectively,
before the indicated steady-state input conditions were
established.
H = high level (steady state), L = low level (steady state)
X = irrelevant (any input, including transitions)
↑ = transition from low to high level
QAn, QGn = the level of QA or QG before the most recent
↑ transition of the clock; indicates a 1-bit shift.A
GNDG
CLR
CLK
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