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SN74AHCT139D-SN74AHCT139DR-SN74AHCT139PWLE Fast Delivery,Good Price
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SN74AHCT139DTIN/a5avaiDual 2-Line To 4-Line Decoders / Demultiplexers
SN74AHCT139DRTIN/a1295avaiDual 2-Line To 4-Line Decoders / Demultiplexers
SN74AHCT139PWLETIN/a1762avaiDual 2-Line To 4-Line Decoders / Demultiplexers


SN74AHCT139PWLE ,Dual 2-Line To 4-Line Decoders / Demultiplexersmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74AHCT14 ,Hex Schmitt-Trigger InvertersTable of Contents9.1 Overview.... 81
SN74AHCT14D ,Hex Schmitt-Trigger InvertersBlock Diagram..... 82 Applications..... 19.3 Feature Description...... 83 Description....... 19.4 D ..
SN74AHCT14DBLE ,Hex Schmitt-Trigger Inverters SCLS246Q–OCTOBER 1995–REVISED JULY 20146 Pin Configuration and FunctionsSN54AHCT14...JORWPACKAGE S ..
SN74AHCT14DBR ,Hex Schmitt-Trigger InvertersElectrical Characteristics....... 513.1 Related Links.. 127.6 Switching Characteristics...... 513.2 ..
SN74AHCT14DBR ,Hex Schmitt-Trigger InvertersFeatures 3 DescriptionThe SNx4AHCT14 devices contain six independent1• Inputs are TTL-Voltage Compa ..
SN74LS796N ,TRI-STATE OCTAL BUFFERS
SN74LS796N ,TRI-STATE OCTAL BUFFERS
SN74LS798N ,TRI-STATE OCTAL BUFFERS
SN74LS83N ,4-BIT BINARY FULL ADDER WITH FAST CARRYSN54/74LS83A4-BIT BINARY FULL ADDERWITH FAST CARRYThe SN54 /74LS83A is a high-speed 4-Bit binary Fu ..
SN74LS85 ,LOW POWER SCHOTTKY
SN74LS85D ,4-BIT MAGNITUDE COMPARATOR


SN74AHCT139D-SN74AHCT139DR-SN74AHCT139PWLE
Dual 2-Line To 4-Line Decoders / Demultiplexers
Cascading and/or Data Reception Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information

The ’AHCT139 devices are dual 2-line to 4-line
decoders/demultiplexers designed for 4.5-V to
5.5-V VCC operation. These devices are
designed to be used in high-performance
memory-decoding or data-routing applications
requiring very short propagation delay times. In
high-performance memory systems, these
decoders can be used to minimize the effects of
system decoding. When used with high-speed
memories utilizing a fast enable circuit, the delay
times of these decoders and the enable time of the
memory usually are less than the typical access
time of the memory. This means that the effective
system delay introduced by the decoders is
negligible.
ORDERING INFORMATION

†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Y0
2Y1
1Y0
1Y1
1Y21GNC
2Y32Y22G
1Y3
GND
SN54AHCT139... FK PACKAGE
(TOP VIEW)

NC – No internal connection
1Y0
1Y1
1Y2
1Y3
GND
2Y0
2Y1
2Y2
2Y3
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