SN74AHCT123ADR ,Dual Retriggerable Monostable Multivibrators/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74AHCT125D ,Quadruple Bus Buffer Gates With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74AHCT125DBLE ,Quadruple Bus Buffer Gates With 3-State Outputs SN54AHCT125, SN74AHCT125 QUADRUPLE BUS BUFFER GATESWITH 3-STATE OUTPUTSSCLS264O − DECEMBER 1995 − ..
SN74AHCT125DBR ,Quadruple Bus Buffer Gates With 3-State Outputslogic diagram (positive logic)11OE2 31A 1Y42OE5 62A 2Y103OE9 83A 3Y134OE11124A 4YPin numbers shown ..
SN74AHCT125DGVR ,Quadruple Bus Buffer Gates With 3-State Outputslogic diagram (positive logic)11OE2 31A 1Y42OE5 62A 2Y103OE9 83A 3Y134OE11124A 4YPin numbers shown ..
SN74AHCT125DR ,Quadruple Bus Buffer Gates With 3-State Outputslogic diagram (positive logic)11OE2 31A 1Y42OE5 62A 2Y103OE9 83A 3Y134OE11124A 4YPin numbers shown ..
SN74LS74AN ,LOW POWER SCHOTTKYq Package Options Include Plastic "Small SN5474 . . .J PACKAGEOutline" Packages. Ceramic Chip Carri ..
SN74LS74ANSR ,Dual D-type pos.-edge-triggered flip-flops with preset and clearq Package Options Include Plastic "Small SN5474 . . .J PACKAGEOutline" Packages. Ceramic Chip Carri ..
SN74LS74N ,DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP
SN74LS75N ,4-BIT D LATCHSN54/74LS754-BIT D LATCHSN54/74LS77The TTL/MSI SN54/74LS75 and SN54/74LS77 are latches used as tem- ..
SN74LS75NSR ,Quad bistable latches
SN74LS75NSR ,Quad bistable latches
SN74AHCT123ADR
Dual Retriggerable Monostable Multivibrators
Retriggerable for Very Long Output Pulses Overriding Clear Terminates Output Pulse Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering informationThese edge-triggered multivibrators feature
output pulse-duration control by three methods. In
the first method, the A input is low, and the B input
goes high. In the second method, the B input is
high, and the A input goes low. In the third method,
the A input is low, the B input is high, and the clear
(CLR) input goes high.
The output pulse duration is programmed by
selecting external resistance and capacitance
values. The external timing capacitor must be
connected between Cext and Rext/Cext (positive)
and an external resistor connected between
Rext/Cext and VCC. To obtain variable pulse
durations, connect an external variable resistance
between Rext/Cext and VCC. The output pulse
duration also can be reduced by taking CLR low.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54AHCT123A... FK PACKAGE
(TOP VIEW)1CLR
2Cextext/Cext
GND
1Cext
2CLR
1Cext
2CLR
1CLR
2Cext1ANC2B1R
GND
NC – No internal connection
ext
ext
ext
ext
