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SN74AHC595D-SN74AHC595DR-SN74AHC595PW-SN74AHC595PWR-SN74AHC595PWRG4 Fast Delivery,Good Price
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SN74AHC595DTI ?N/a393avai8-Bit Shift Registers With 3-State Output Registers
SN74AHC595DRTI ?N/a2500avai8-Bit Shift Registers With 3-State Output Registers
SN74AHC595DRTIN/a1736avai8-Bit Shift Registers With 3-State Output Registers
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SN74AHC595PWRTIN/a11601avai8-Bit Shift Registers With 3-State Output Registers
SN74AHC595PWRTEXASINSTRUMN/a4000avai8-Bit Shift Registers With 3-State Output Registers
SN74AHC595PWRG4TEXASINSTRUMN/a4000avai8-Bit Shift Registers With 3-State Output Registers 16-TSSOP -40 to 125


SN74AHC595PW ,8-Bit Shift Registers With 3-State Output RegistersMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV S ..
SN74AHC595PWR ,8-Bit Shift Registers With 3-State Output RegistersFeatures 3 DescriptionThe SN74AHC595 device contains an 8-bit serial-in,1• Operating Range: 2-V to ..
SN74AHC595PWR ,8-Bit Shift Registers With 3-State Output RegistersTable of Contents8.1 Overview.. 131
SN74AHC595PWRG4 ,8-Bit Shift Registers With 3-State Output Registers 16-TSSOP -40 to 125Block Diagram... 132 Applications..... 18.3 Feature Description.... 143 Description....... 18.4 Dev ..
SN74AHC74 ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and PresetMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)UNITSupply volt ..
SN74AHC74D ,Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and PresetMaximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functio ..
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SN74AHC595D-SN74AHC595DR-SN74AHC595PW-SN74AHC595PWR-SN74AHC595PWRG4
8-Bit Shift Registers With 3-State Output Registers
SRCLR
RCLK
SRCLK
SER Q

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SN74AHC595

SCLS373K –MAY 1996–REVISED SEPTEMBER 2015
SN74AHC595 8-Bit Shift Registers With 3-State Output Registers Features 3 Description

The SN74AHC595 device contains an 8-bit serial-in, Operating Range: 2-Vto 5.5-V VCC parallel-out shift register that feeds an 8-bit D-type• 8-Bit Serial-In, Parallel-Out Shift storage register. The storage register has parallel3-• Latch-Up Performance Exceeds 100 mA Per state outputs. Separate clocks are provided for both
JESD 78, ClassII the shift and storage registers. The shift register has direct overriding clear (SRCLR) input,a serial• ESD Protection Exceeds JESD22 (SER) input, anda serial output for cascading. When– 2000-V Human-Body Model (A114-A) the output-enable (OE) inputis high, all outputs– 200-V Machine Model (A115-A) except QH′ arein the high-impedance state. 1000-V Charged-Device Model (C101) Device Information2 Applications• Network Switches• Power Infrastructures• LED Displays• Servers
(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Logic Diagram (Positive Logic)
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