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Partno Mfg Dc Qty AvailableDescript
SN74AHC373DBRTIN/a180avaiOctal Transparent D-Type Latches With 3-State Outputs
SN74AHC373DWTIN/a173avaiOctal Transparent D-Type Latches With 3-State Outputs
SN74AHC373DWRTIN/a17264avaiOctal Transparent D-Type Latches With 3-State Outputs
SN74AHC373NTIN/a198avaiOctal Transparent D-Type Latches With 3-State Outputs
SN74AHC373NSRTIN/a98avaiOctal Transparent D-Type Latches With 3-State Outputs
SN74AHC373PWTIN/a3065avaiOctal Transparent D-Type Latches With 3-State Outputs
SN74AHC373PWRTI N/a11500avaiOctal Transparent D-Type Latches With 3-State Outputs


SN74AHC373DWR ,Octal Transparent D-Type Latches With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74AHC373N ,Octal Transparent D-Type Latches With 3-State Outputslogic diagram (positive logic)1OE11LEC121Q31D1DTo Seven Other Channels†absolute
SN74AHC373NSR ,Octal Transparent D-Type Latches With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74AHC373PW ,Octal Transparent D-Type Latches With 3-State Outputs SN54AHC373, SN74AHC373 OCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCLS235I – OCTOBER 1995 ..
SN74AHC373PWR ,Octal Transparent D-Type Latches With 3-State Outputs/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74AHC373PWRG4 , OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
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SN74LS645 ,OCTAL BUS TRANSCEIVERS
SN74LS645-1NSR ,Octal bus transceivers
SN74LS645DW ,OCTAL BUS TRANSCEIVERS
SN74LS645NSR ,Octal bus transceivers


SN74AHC373DBR-SN74AHC373DW-SN74AHC373DWR-SN74AHC373N-SN74AHC373NSR-SN74AHC373PW-SN74AHC373PWR
Octal Transparent D-Type Latches With 3-State Outputs
description/ordering information
The ’AHC373 devices are octal transparent D-type latches designed for 2-V to 5.5-V VCC operation.
When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs
are latched at the logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
ORDERING INFORMATION

†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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