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SN74ACT7803-15DL |SN74ACT780315DLTIN/a47avai512 x 18 synchronous FIFO memory
SN74ACT7803-25DL |SN74ACT780325DLTIN/a611avai512 x 18 synchronous FIFO memory


SN74ACT7803-25DL ,512 x 18 synchronous FIFO memory SN74ACT7803 512 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS191C – MARCH 1991 – REVISED APRIL 1998 ..
SN74ACT7806-20DL ,256 x 18 asynchronous FIFO memory SN74ACT7806 256 × 18STROBED FIRST-IN, FIRST-OUT MEMORYSCAS438C – APRIL 1992 – REVISED APRIL 1998DL ..
SN74ACT7806-40DL ,256 x 18 asynchronous FIFO memory SN74ACT7806 256 × 18STROBED FIRST-IN, FIRST-OUT MEMORYSCAS438C – APRIL 1992 – REVISED APRIL 1998DL ..
SN74ACT7806-40DLR , 256 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7808-25FN ,2048 X 9 asynchronous FIFO memory SN74ACT7808 2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS205E – FEBRUARY 1991 – REVISED NOVEMBE ..
SN74ACT7808-40FN ,2048 X 9 asynchronous FIFO memory SN74ACT7808 2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS205E – FEBRUARY 1991 – REVISED NOVEMBE ..
SN74LS27DR ,Triple 3-input positive-NOR gates
SN74LS28 ,QUADRUPLE 2-INPUT POSITIVE-NOR BUFFERS
SN74LS280J ,9-bit odd/even parity generators / checkers
SN74LS280J ,9-bit odd/even parity generators / checkers
SN74LS280J ,9-bit odd/even parity generators / checkers
SN74LS280N ,9-BIT ODD/EVEN PARITY GENERATORS/CHECKERSSN54/74LS2809-BIT ODD/EVEN PARITYGENERATORS/CHECKERSThe SN54/74LS280 is a Universal 9-Bit Parity Ge ..


SN74ACT7803-15DL-SN74ACT7803-25DL
512 x 18 synchronous FIFO memory
to Independent System Clocks Input-Ready Flag Synchronized to Write
Clock
Output-Ready Flag Synchronized to Read
Clock
512 Words by 18 Bits Low-Power Advanced CMOS Technology Half-Full Flag and Programmable
Almost-Full/Almost-Empty Flag
Bidirectional Configuration and Width
Expansion Without Additional Logic
Fast Access Times of 12 ns With a 50-pF
Load and All Data Outputs Switching
Simultaneously
Data Rates up to 67 MHz Pin-to-Pin Compatible With SN74ACT7805
and SN74ACT7813
Packaged in Shrink Small-Outline 300-mil
Package Using 25-mil Center-to-Center
Spacing
description

The SN74ACT7803 is a 512-word × 18-bit FIFO
suited for buffering asynchronous datapaths up to
67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering
without additional logic. Multiple distributed VCC and GND pins, along with Texas Instruments patented output
edge control (OEC) circuit, dampen simultaneous switching noise.
The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident.
Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input
ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low
and output ready (OR) is high. The first word written to memory is clocked through to the output buffer,
regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output
buffer.
The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four
WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes
the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be
reset upon power up.
The SN74ACT7803 is characterized for operation from 0°C to 70°C.
D16
D15
D14
D13
D12
D11
D10
VCC
GND
PEN
AF/AE
WRTCLK
WRTEN2
WRTEN1
Q16
Q15
GND
Q14CC
Q13
Q12
Q11
Q10
GNDCC
GND
RDCLK
RDEN
OE2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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