SN74ACT533DW ,Octal Transparent D-Type Latches With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ACT533PWR ,Octal Transparent D-Type Latches With 3-State Outputs SN54ACT533, SN74ACT533 OCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCAS553C – NOVEMBER 199 ..
SN74ACT534DBR ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ACT534DW ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ACT534DWR ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs SN54ACT534, SN74ACT534 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH 3-STATE OUTPUTSSCAS556C – NOVEMB ..
SN74ACT534PWR ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74LS259 ,8-Bit Adder LatchFUNCTIONAL DESCRIPTIONThe SN74LS259 has four modes of operation as shown in other inputs in the LOW ..
SN74LS259B ,Octal addressable latches
SN74LS259B ,Octal addressable latches
SN74LS259BDR ,Octal addressable latches
SN74LS259ML1 ,8-Bit Addressable LatchFUNCTIONAL DESCRIPTIONThe SN74LS259 has four modes of operation as shown in other inputs in the LOW ..
SN74LS259MR1 ,8-Bit Addressable Latch3SN74LS259DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)LimitsSym ..
SN74ACT533DW-SN74ACT533PWR
Octal Transparent D-Type Latches With 3-State Outputs
3-State Inverting Outputs Drive Bus LinesDirectly
description/ordering informationThe ’ACT533 devices are octal transparent
D-type latches with 3-state outputs. When the
latch-enable (LE) input is high, the Q outputs
follow the complements of the data (D) inputs.
When LE is taken low, the Q outputs are latched
at the inverted levels set up at the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without need for interface or pullup
components.
OE does not affect the internal operations of the
latches. Old data can be retained or new data can
be entered while the outputs are in the
high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
GND
SN54ACT533... FK PACKAGE
(TOP VIEW)1QOE
GND
