SN74AC564N ,Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74AC564PWR ,Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs SCAS551D− NOVEMBER 1995 − R ..
SN74AC573DBRG4 ,Octal D-Type Transparent Latches With 3-State Outputs 20-SSOP -40 to 85maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74AC573DW ,Octal D-Type Transparent Latches With 3-State OutputsSN54AC573, SN74AC573OCTAL D-TYPE TRANSPARENT LATCHESWITH 3-STATE OUTPUTSSCAS542D - OCTOBER 1995 − ..
SN74AC573DWG4 ,Octal D-Type Transparent Latches With 3-State Outputs 20-SOIC -40 to 85maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74AC573N ,Octal D-Type Transparent Latches With 3-State OutputsSN54AC573, SN74AC573OCTAL D-TYPE TRANSPARENT LATCHESWITH 3-STATE OUTPUTSSCAS542D - OCTOBER 1995 − ..
SN74LS193D ,PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER
SN74LS193J ,Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear
SN74LS193J ,Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear
SN74LS193J ,Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear
SN74LS193J ,Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear
SN74LS193N ,PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERSN54/74LS192SN54/74LS193PRESETTABLE BCD/DECADEUP/DOWN COUNTERPRESETTABLE 4-BIT BINARYPRESETTABLE BC ..
SN74AC564N-SN74AC564PWR
Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs
Directly Full Parallel Access for Loading Flow-Through Architecture to Optimize
PCB Layout
description/ordering informationThe ’AC564 devices are octal D-type
edge-triggered flip-flops that feature inverting
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input,
the Q outputs are set to the inverse logic levels set
up at the data (D) inputs.
A buffered output-enable (OE) input places the
eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In
the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
interface or pullup components.
OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
