SN74AC534DBR ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74AC534PW ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74AC563N ,Octal D-Type Transparent Latches With 3-State Outputs SCAS552C − NOVEMBER 1995 − REV ..
SN74AC564N ,Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74AC564PWR ,Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs SCAS551D− NOVEMBER 1995 − R ..
SN74AC573DBRG4 ,Octal D-Type Transparent Latches With 3-State Outputs 20-SSOP -40 to 85maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LS193D ,PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER
SN74LS193J ,Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear
SN74LS193J ,Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear
SN74LS193J ,Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear
SN74LS193J ,Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear
SN74LS193N ,PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERSN54/74LS192SN54/74LS193PRESETTABLE BCD/DECADEUP/DOWN COUNTERPRESETTABLE 4-BIT BINARYPRESETTABLE BC ..
SN74AC534-SN74AC534DBR-SN74AC534PW
Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs
Directly Full Parallel Access for Loading
description/ordering informationThese octal edge-triggered D-type flip-flops
feature 3-state outputs designed specifically for
driving highly capacitive or relatively
low-impedance loads. The devices are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
On the positive transition of the clock (CLK) input,
the Q outputs are set to the complements of the
logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without need for interface or pullup
components.
OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
