SN74AC533DBR ,Octal Transparent D-Type Latches With 3-State Outputs SCAS555C − NOVEMBER 1995 − REVI ..
SN74AC534 ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs SCAS554D − NOVEMBER 1995 − REV ..
SN74AC534DBR ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74AC534PW ,Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74AC563N ,Octal D-Type Transparent Latches With 3-State Outputs SCAS552C − NOVEMBER 1995 − REV ..
SN74AC564N ,Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LS193D ,PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER
SN74LS193J ,Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear
SN74LS193J ,Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear
SN74LS193J ,Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear
SN74LS193J ,Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear
SN74LS193N ,PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERSN54/74LS192SN54/74LS193PRESETTABLE BCD/DECADEUP/DOWN COUNTERPRESETTABLE 4-BIT BINARYPRESETTABLE BC ..
SN74AC533DBR
Octal Transparent D-Type Latches With 3-State Outputs
Directly Full Parallel Access for Loading
description/ordering informationThe ’AC533 devices are octal transparent D-type
latches with 3-state outputs. When the
latch-enable (LE) input is high, the Q outputs
follow the complements of the data (D) inputs.
When LE is taken low, the Q outputs are latched
at the inverse logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without need for interface or pullup
components.
OE does not affect the internal operations of the
latches. Old data can be retained or new data can
be entered while the outputs are in the
high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
