SN74ABT823DWR ,9-Bit Bus-Interface Flip-Flops With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ABT8245 ,Scan Test Devices With Octal Bus Transceivers SN54ABT8245, SN74ABT8245 SCAN TEST DEVICESWITH OCTAL BUS TRANSCEIVERSSCBS124D – AUGUST 1992 – REVI ..
SN74ABT8245DW ,Scan Test Devices With Octal Bus Transceivers SN54ABT8245, SN74ABT8245 SCAN TEST DEVICESWITH OCTAL BUS TRANSCEIVERSSCBS124D – AUGUST 1992 – REVI ..
SN74ABT827DB , 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74ABT827DBR ,10-Bit Buffers/Drivers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ABT827DW ,10-Bit Buffers/Drivers With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LS158NSR ,Quadruple 2-Line To 1-Line Data Selectors/Multiplexers
SN74LS158NSR ,Quadruple 2-Line To 1-Line Data Selectors/Multiplexers
SN74LS15N ,TRIPLE 3-INPUT AND GATE
SN74LS15N ,TRIPLE 3-INPUT AND GATE
SN74LS15N ,TRIPLE 3-INPUT AND GATE
SN74LS15N ,TRIPLE 3-INPUT AND GATE
SN74ABT823DBR-SN74ABT823DWR
9-Bit Bus-Interface Flip-Flops With 3-State Outputs
Latch-Up Performance Exceeds 500 mA PerJEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C High-Impedance State During Power Up
and Power Down High-Drive Outputs (–32-mA IOH, 64-mA IOL) Buffered Control Inputs to Reduce
dc Loading Effects Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, Ceramic Chip
Carriers (FK) and Flatpacks (W), and
Standard Plastic (NT) and Ceramic (JT)
DIPs
descriptionThese 9-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
With the clock-enable (CLKEN) input low, the nine
D-type edge-triggered flip-flops enter data on the
low-to-high transitions of the clock. Taking CLKEN
high disables the clock buffer, thus latching the
outputs. Taking the clear (CLR) input low causes
the nine Q outputs to go low, independently of the
clock.
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high
or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT823 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT823 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ABT823... FK PACKAGE
(TOP VIEW)CLR
GND
CLK
CLKEN1DOENC 1Q2Q
GND
CLKEN
CLK
NC – No internal connection
