SN74ABT821ADWR ,10-Bit Bus Interface Flip-Flops With 3-State Outputs SN54ABT821, SN74ABT821A 10-BIT BUS-INTERFACE FLIP-FLOPSWITH 3-STATE OUTPUTSSCBS193E – FEBRUARY 199 ..
SN74ABT823DBR ,9-Bit Bus-Interface Flip-Flops With 3-State Outputs SN54ABT823, SN74ABT823 9-BIT BUS-INTERFACE FLIP-FLOPSWITH 3-STATE OUTPUTSSCBS158E – JANUARY 1991 – ..
SN74ABT823DWR ,9-Bit Bus-Interface Flip-Flops With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ABT8245 ,Scan Test Devices With Octal Bus Transceivers SN54ABT8245, SN74ABT8245 SCAN TEST DEVICESWITH OCTAL BUS TRANSCEIVERSSCBS124D – AUGUST 1992 – REVI ..
SN74ABT8245DW ,Scan Test Devices With Octal Bus Transceivers SN54ABT8245, SN74ABT8245 SCAN TEST DEVICESWITH OCTAL BUS TRANSCEIVERSSCBS124D – AUGUST 1992 – REVI ..
SN74ABT827DB , 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74LS158N ,QUAD 2-INPUT MULTIPLEXERSN54/74LS158QUAD 2-INPUT MULTIPLEXERThe LSTTL/MSI SN54L/ 74LS158 is a high speed Quad 2-input Multi ..
SN74LS158NSR ,Quadruple 2-Line To 1-Line Data Selectors/Multiplexers
SN74LS158NSR ,Quadruple 2-Line To 1-Line Data Selectors/Multiplexers
SN74LS15N ,TRIPLE 3-INPUT AND GATE
SN74LS15N ,TRIPLE 3-INPUT AND GATE
SN74LS15N ,TRIPLE 3-INPUT AND GATE
SN74ABT821A-SN74ABT821ADBR-SN74ABT821ADW-SN74ABT821ADWR
10-Bit Bus Interface Flip-Flops With 3-State Outputs
JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C High-Impedance State During Power Up
and Power Down High-Drive Outputs (–32-mA IOH, 64-mA IOL) Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, Ceramic Chip
Carriers (FK), Ceramic Flat (W) Package,
and Plastic (NT) and Ceramic (JT) DIPs
descriptionThese 10-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
The ten flip-flops are edge-triggered D-type
flip-flops. On the positive transition of the clock
(CLK) input, the devices provide true data at the
Q outputs.
A buffered output-enable (OE) input can be used
to place the ten outputs in either a normal logic
state (high or low logic levels) or a high-impe-
dance state. In the high-impedance state, the
outputs neither load nor drive the bus lines
significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without need for interface or pullup
components.
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can
be entered while the outputs are in the high-impedance state.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT821 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT821A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ABT821... FK PACKAGE
(TOP VIEW)10D
GND
10Q
CLK
10D
GND
CLK10Q1DOENC 1Q2Q
NC – No internal connection
