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Partno Mfg Dc Qty AvailableDescript
SN74ABT377ATIN/a400avaiOctal Edge-Triggered D-Type Flip-Flops With Clock Enable
SN74ABT377ADBLETIN/a615avaiOctal Edge-Triggered D-Type Flip-Flops With Clock Enable
SN74ABT377ADBRTIN/a3820avaiOctal Edge-Triggered D-Type Flip-Flops With Clock Enable
SN74ABT377ADWTIN/a200avaiOctal Edge-Triggered D-Type Flip-Flops With Clock Enable
SN74ABT377ADWRTIN/a39960avaiOctal Edge-Triggered D-Type Flip-Flops With Clock Enable
SN74ABT377APWTIN/a101avaiOctal Edge-Triggered D-Type Flip-Flops With Clock Enable


SN74ABT377ADWR ,Octal Edge-Triggered D-Type Flip-Flops With Clock Enablemaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ABT377APW ,Octal Edge-Triggered D-Type Flip-Flops With Clock Enablemaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ABT377DWR , OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
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SN74ABT540DW ,Octal Buffers/Drivers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
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SN74LS14N ,SCHMITT TRIGGERS DUAL GATE/HEX INVERTERSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN5414,SN54LS14,SN74 ..
SN74LS14NSR ,Hex schmitt-trigger inverters 14-SO 0 to 70Sample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN5414,SN54LS14,SN74 ..
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SN74ABT377A-SN74ABT377ADBLE-SN74ABT377ADBR-SN74ABT377ADW-SN74ABT377ADWR-SN74ABT377APW
Octal Edge-Triggered D-Type Flip-Flops With Clock Enable
at VCC = 5 V, TA = 25°C High-Drive Outputs (–32-mA IOH, 64-mA IOL) ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Plastic (N) and Ceramic (J) DIPs, and
Ceramic Flat (W) Package
description

These 8-bit positive-edge-triggered D-type
flip-flops with a clock (CLK) input are particularly
suitable for implementing buffer and storage
registers, shift registers, and pattern generators.
Data (D) input information that meets the setup
time requirements is transferred to the Q outputs
on the positive-going edge of the clock pulse if the
common clock-enable (CLKEN) input is low.
Clock triggering occurs at a particular voltage
level and is not directly related to the transition
time of the positive-going pulse. When the
buffered clock (CLK) input is at either the high or
low level, the D-input signal has no effect at the
output. The circuits are designed to prevent false
clocking by transitions at CLKEN.
The SN54ABT377 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT377A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ABT377... FK PACKAGE
(TOP VIEW)

GND
CLK1QCLKEN
GND
CLK
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