SN74ABT373DBR ,Octal Transparent D-Type Latches With 3-State Outputs SN54ABT373, SN74ABT373 OCTAL TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTSSCBS155D – JANUARY 1991 ..
SN74ABT373DW ,Octal Transparent D-Type Latches With 3-State Outputslogic diagram (positive logic)1OE11LEC121Q31D1DTo Seven Other Channels‡absolute
SN74ABT373DWR ,Octal Transparent D-Type Latches With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ABT373N ,Octal Transparent D-Type Latches With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ABT373NSR ,Octal Transparent D-Type Latches With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ABT373PW ,Octal Transparent D-Type Latches With 3-State Outputslogic diagram (positive logic)1OE11LEC121Q31D1DTo Seven Other Channels‡absolute
SN74LS145DR ,BCD-To-Decimal Decoders/Drivers
SN74LS145DR ,BCD-To-Decimal Decoders/Drivers
SN74LS147N ,10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS
SN74LS148DR2 ,10-Line-to-4-Line and 8-Line-to-3-Line Priority Encodersorder data line is encoded. Both devices have data inputs and outputswhich are active at the low lo ..
SN74LS148J ,8-line to 3-line priority encoder ..
SN74LS148J ,8-line to 3-line priority encoder ..
SN74ABT373DBLE-SN74ABT373DBR-SN74ABT373DW-SN74ABT373DWR-SN74ABT373N-SN74ABT373NSR-SN74ABT373PW-SN74ABT373PWR
Octal Transparent D-Type Latches With 3-State Outputs
at VCC = 5 V, TA = 25°C High-Drive Outputs (–32-mA IOH, 64-mA IOL) Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (N)
and Ceramic (J) DIPs
descriptionThe eight latches of the ’ABT373 are transparent
D-type latches. While the latch-enable (LE) input
is high, the Q outputs follow the data (D) inputs.
When LE is taken low, the Q outputs are latched
at the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or a
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without need for interface or pullup
components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT373 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT373 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each latch)Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ABT373... FK PACKAGE
(TOP VIEW)GND1QOE5D
GND
