SN74ABT16843DLR ,18-Bit Bus-Interface D-Type Latches With 3-State Outputs SN54ABT16843, SN74ABT16843 18-BIT BUS-INTERFACE D-TYPE LATCHESWITH 3-STATE OUTPUTSSCBS223E – OCTOB ..
SN74ABT16863DL ,18-Bit Bus Transceivers With 3-State Outputs SN54ABT16863, SN74ABT16863 18-BIT BUS TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS225C – JUNE 1992 – REVIS ..
SN74ABT16952 ,16-Bit Registered Transceivers With 3-State Outputs SN54ABT16952, SN74ABT16952 16-BIT REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS082C – FEBRUARY 1 ..
SN74ABT16952DGGR ,16-Bit Registered Transceivers With 3-State Outputs SN54ABT16952, SN74ABT16952 16-BIT REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS082C – FEBRUARY 1 ..
SN74ABT16952DGGR ,16-Bit Registered Transceivers With 3-State Outputs SN54ABT16952, SN74ABT16952 16-BIT REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS082C – FEBRUARY 1 ..
SN74ABT16952DL ,16-Bit Registered Transceivers With 3-State Outputs SN54ABT16952, SN74ABT16952 16-BIT REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS082C – FEBRUARY 1 ..
SN74LS125A ,LOW POWER SCHOTTKYmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LS125AD ,Quad 3-state buffermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LS125ADBR ,Quadruple Bus Buffers With 3-State Outputslogic diagram (each gate)’125, ’LS125AGAY’126, ’LS126AGAYY = A2POST OFFICE BOX 655303 • DALLAS, TEX ..
SN74LS125ADBR ,Quadruple Bus Buffers With 3-State Outputsmaximum ratings over operating free-air temperature (unless otherwise noted)(’125 and ’126) Supply ..
SN74LS125ADR ,Quadruple Bus Buffers With 3-State OutputsSN54125, SN54126, SN54LS125A, SN54LS126A, SN74125, SN74126, SN74LS125A, SN74LS126AThe SN54125, SN54 ..
SN74LS125AML1 ,Quad 3-State Buffers
SN74ABT16843DLR
18-Bit Bus-Interface D-Type Latches With 3-State Outputs
Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB
Layout High-Impedance State During Power Up
and Power Down High-Drive Outputs (–32-mA IOH, 64-mA IOL) Package Options Include Plastic Thin
Shrink Small-Outline (DGG), 300-mil Shrink
Small-Outline (DL) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
descriptionThe ’ABT16843 18-bit bus-interface D-type
latches are designed specifically for driving highly
capacitive or relatively low-impedance loads.
They are particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The ’ABT16843 can be used as two 9-bit latches
or one 18-bit latch. The 18 latches are transparent
D-type latches. The device provides true data at
its outputs.
A buffered output-enable (OE) input can be used
to place the nine outputs in either a normal logic
state (high or low logic levels) or a
high-impedance state. The outputs are in the
high-impedance state during power up and power
down. The outputs remain in the high-impedance
state while the device is powered down. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
need for interface or pullup components.
1Q1
GND
1Q2
1Q3CC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2OE
2CLR
1D1
GND
1D2
1D3CC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2PRE
2LE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
