SN74ABT16657DGGR ,16-Bit Transceivers With Parity Generators / Checkers And 3-State Outputs SN54ABT16657, SN74ABT16657 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERSAND 3-STATE OUTPUTSS ..
SN74ABT16657DL ,16-Bit Transceivers With Parity Generators / Checkers And 3-State Outputs SN54ABT16657, SN74ABT16657 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERSAND 3-STATE OUTPUTSS ..
SN74ABT16657DL ,16-Bit Transceivers With Parity Generators / Checkers And 3-State Outputs SN54ABT16657, SN74ABT16657 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERSAND 3-STATE OUTPUTSS ..
SN74ABT16657DLR ,16-Bit Transceivers With Parity Generators / Checkers And 3-State Outputs SN54ABT16657, SN74ABT16657 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERSAND 3-STATE OUTPUTSS ..
SN74ABT16821 ,20-Bit Bus Interface Flip-Flops With 3-State Outputslogic diagram (positive logic)11OE561CLKOne of TenChannelsC12551Q11D11DTo Nine Other Channels282OE2 ..
SN74ABT16821DGGR ,20-Bit Bus Interface Flip-Flops With 3-State Outputs SN54ABT16821, SN74ABT16821 20-BIT BUS-INTERFACE FLIP-FLOPSWITH 3-STATE OUTPUTSSCBS216B – JUNE 1992 ..
SN74LS122NSR ,Retriggerable monostable multivibrator
SN74LS122NSR ,Retriggerable monostable multivibrator
SN74LS123 ,RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
SN74LS123D ,RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
SN74LS123DR2 ,RE Trigger Monostable MultivibratorSN74LS122, SN74LS123Retriggerable MonostableMultivibratorsThese dc triggered multivibrators feature ..
SN74LS123DR2 ,RE Trigger Monostable Multivibrator3SN74LS122, SN74LS123WAVEFORMSRETRIGGER(See Application Data)PULSEB INPUTQ OUTPUTt OUTPUT WITHOUT R ..
SN74ABT16657DGGR-SN74ABT16657DL-SN74ABT16657DLR
16-Bit Transceivers With Parity Generators / Checkers And 3-State Outputs 56-TSSOP -40 to 85
JEDEC Standard JESD-17 Typical V OLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB
Layout High-Drive Outputs (–32-mA IOH, 64-mA IOL) Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
descriptionThe ’ABT16657 contain two noninverting octal
transceiver sections with separate parity
generator/checker circuits and control signals.
For either section, the transmit/receive (1T/R or
2T/R) input determines the direction of data flow.
When 1T/R (or 2T/R) is high, data flows from the
1A (or 2A) port to the 1B (or 2B) port (transmit
mode); when 1T/R (or 2T/R) is low, data flows
from the 1B (or 2B) port to the 1A (or 2A) port
(receive mode). When the output-enable (1OE or
2OE) input is high, both the 1A (or 2A) and 1B (or
2B) ports are in the high-impedance state.
Odd or even parity is selected by a logic high or low level, respectively, on the 1ODD/EVEN (or 2ODD/EVEN)
input. 1PARITY (or 2PARITY) carries the parity bit value; it is an output from the parity generator/checker in the
transmit mode and an input to the parity generator/checker in the receive mode.
In the transmit mode, after the 1A (or 2A) bus is polled to determine the number of high bits, 1PARITY (or
2PARITY) is set to the logic level that maintains the parity sense selected by the level at the 1ODD/EVEN (or
2ODD/EVEN) input. For example, if 1ODD/EVEN is low (even parity selected) and there are five high bits on
the 1A bus, then 1PARITY is set to the logic high level so that an even number of the nine total bits (eight 1A-bus
bits plus parity bit) are high.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1ERR
GND
1A1
1A2CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6CC
2A7
2A8
GND
2ERR
2OE
1PARITY
GND
1B1
1B2CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6CC
2B7
2B8
GND
2PARITY
2ODD/EVEN
2T/R
NC – No internal connection
