SN74ABT162827ADL ,20-Bit Buffers/Drivers With 3-State Outputs/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74ABT162841DL ,20-Bit Bus-Interface D-Type Latches With 3-State Outputs/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74ABT16373 ,16-Bit Transparent D-Type Latches With 3-State Outputs 48-SSOP -40 to 85
SN74ABT16373 ,16-Bit Transparent D-Type Latches With 3-State Outputs 48-SSOP -40 to 85
SN74ABT16373A ,16-Bit Transparent D-Type Latches With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ABT16373ADGGR ,16-Bit Transparent D-Type Latches With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74LS109ANSR ,Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset
SN74LS109ANSR ,Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset
SN74LS10D ,TRIPLE 3-INPUT NAND GATE
SN74LS10D ,TRIPLE 3-INPUT NAND GATE
SN74LS11 ,Triple 3-input positive-AND gates
SN74LS11 ,Triple 3-input positive-AND gates
SN74ABT162827A-SN74ABT162827ADGGR-SN74ABT162827ADL
20-Bit Buffers/Drivers With 3-State Outputs
High-Impedance State During Power Upand Power Down Typical V OLP (Output Ground Bounce)
<1 V at V CC = 5 V, TA = 25°C Distributed VCC and GND Pins Minimize
High-Speed Switching NoiseIoff and Power-Up 3-State Support Hot
Insertion Flow-Through Architecture Optimizes PCB
Layout Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17 ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
description/ordering informationThe ’ABT162827A devices are noninverting
20-bit buffers composed of two 10-bit buffers with
separate output-enable signals. For either 10-bit
buffer, the two output-enable (1OE1 and 1OE2, or
2OE1 and 2OE2) inputs must both be low for the
corresponding Y outputs to be active. If either
output-enable input is high, the outputs of that
10-bit buffer are in the high-impedance state.
The outputs, which are designed to source or sink
up to 12 mA, include equivalent 25-Ω series
resistors to reduce overshoot and undershoot.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
1Y2
GND
1Y3
1Y4CC
1Y5
1Y6
1Y7
GND
1Y8
1Y9
1Y10
2Y1
2Y2
2Y3
GND
2Y4
2Y5
2Y6
VCC
2Y7
2Y8
GND
2Y9
2Y10
2OE1
1A2
GND
1A3
1A4CC
1A5
1A6
1A7
GND
1A8
1A9
1A10
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2A9
2A10
2OE2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
