SN74ABT162500DL ,18-Bit Universal Bus Transceivers With 3-State Outputs SN54ABT162500, SN74ABT162500 18-BIT UNIVERSAL BUS TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS242E – JUNE ..
SN74ABT162501DL , 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74ABT162601 ,18-Bit Universal Bus Transceivers With 3-State Outputs SN54ABT162601, SN74ABT162601 18-BIT UNIVERSAL BUS TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS247G – AUGUS ..
SN74ABT162601DGGR ,18-Bit Universal Bus Transceivers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ABT162601DL , 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74ABT162601DL , 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74LS107ANSR ,Dual J-K Flip-Flops With Clear
SN74LS109A ,LOW POWER SCHOTTKY
SN74LS109ANSR ,Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset
SN74LS109ANSR ,Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset
SN74LS10D ,TRIPLE 3-INPUT NAND GATE
SN74LS10D ,TRIPLE 3-INPUT NAND GATE
SN74ABT162500DL
18-Bit Universal Bus Transceivers With 3-State Outputs 56-SSOP -40 to 85
State-of-the-Art EPIC-ΙΙB BiCMOS DesignSignificantly Reduces Power Dissipation UBT (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 5 V, TA = 25°C High-Impedance State During Power Up
and Power Down Flow-Through Architecture Optimizes PCB
Layout Latch-Up Performance Exceeds 500 mA
Per JESD 17 ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Shrink
Small-Outline (DL) Package and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
descriptionThese 18-bit universal bus transceivers combine
D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs.
For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the
A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the
latch/flip-flop on the high-to-low transition of CLKAB. Output-enable OEAB is active high. When OEAB is high,
the outputs are active. When OEAB is low, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors
to reduce overshoot and undershoot.
GNDCC
GND
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
GNDCC
GND
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
