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SN65MLVD047DR-SN65MLVD047PW-SN65MLVD047PWR
Multipoint-LVDS Quad Differential Line Driver
www.ti.com
FEATURES DESCRIPTION
APPLICATIONS
LOGIC DIAGRAM (POSITIVE LOGIC)
SN65MLVD047SLLS606A–MARCH 2004–REVISED JULY 2005
MULTIPOINT-LVDS QUAD DIFFERENTIAL LINE DRIVER Differential Line Drivers for 30-Ωto 55-Ω The SN65MLVD047isa quadruple line driver. The
Loads and Data Rates(1) Upto 200 Mbps, output currentof this device has been increased,in
Clock Frequencies upto 100 MHz comparisonto standard LVDS compliant devices,in
orderto support doubly terminated transmission lines•
Supports Multipoint Bus Architectures and heavily loaded backplane bus applications.•
Operates froma Single 3.3-V Supply Backplane applications generally require impedance•
Characterized for Operationto matching termination resistorsat both endsof the
85°C bus. The effective impedanceofa doubly terminated as low as 30 Ω due to the bus•
16-Pin SOIC (JEDEC MS-012) as the capacitive loadof bus
TSSOP (JEDEC MS-153) Packaging drivers allow for as low as 30 Ω. The allow for multiple driversto•
Clock Distribution bus. Driver edge rate controlis•
Backplaneor Cabled Multipoint Data Trans- support operation. The
missionin Telecommunications, 9-kV ESD protection onall
Industrial, and Other Computer Systems Cellular Base Stations Central-Office and PBX Switching Bridges and Routers Low-Power High-Speed Short-Reach
tiveto TIA/EIA-485(1)(1) The data rateofa lineisthe numberof voltage
are madeper second expressedinthe units
second).
