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SN65LVDT32B-SN65LVDT32BDR
Quad LVDS Receiver with -2 to 4.4V Common-mode Range
www.ti.com
FEATURESGND
VCC
SN65LVDT32B
D PACKAGE
(TOP VIEW)
SN65LVDS32B
Logic Diagram
(positive logic)
SN65LVDT32B
ONLY (4 Places)1,2EN
VCC
3,4EN
SN65LVDT3486B
D PACKAGE
(TOP VIEW)
SN65LVDS3486B
Logic Diagram
(positive logic)
SN65LVDT3486B
ONLY (4 Places)
1,2EN
SN65LVDS32B,, SN65LVDT32B
SN65LVDS3486B, SN65LVDT3486B
SN65LVDS9637B, SN65LVDT9637B
SLLS440B–OCTOBER 2000–REVISED APRIL 2007
HIGH-SPEED DIFFERENTIAL RECEIVERS Meetsor Exceeds the Requirementsof ANSI
EIA/TIA-644 Standard for Signaling Rates(1)
up 400 Mbps Operates Witha Single 3.3-V Supply –2-Vto 4.4-V Common-Mode Input Voltage
Range Differential Input Thresholds <50 mV With mVof Hysteresis Over Entire Common-
Mode Input Voltage Range Integrated 110-Ω Line Termination Resistors
Offered With the LVDT Series Propagation Delay Times4ns (typ) Active Fail Safe Assuresa High-Level Output
With No Input Bus-Pin ESD Protection Exceeds 15 kV HBM Inputs Remain High-Impedance on Power
Down Recommended Maximum Parallel Rateof
200 M-Transfer/s Availablein Small-Outline Package With
1,27-mm Terminal Pitch
Pin-Compatible With the AM26LS32, MC3486, µA9637
