SN65LVDS94DGGRG4 ,Serdes (Serializer/Deserializer) Receiver 56-TSSOP -40 to 85BLOCK DIAGRAMSerial-In/Parallel-OutShift RegisterA0PD0Serial In A,B, ...GD1A0MCLK D2D3D4D6D7Serial- ..
SN65LVDS95DGG ,Serdes (Serializer/Deserializer) TransmitterMAXIMUM RATINGS(1)over operating free-air temperature range (unless otherwise noted)UNIT(2)V Supply ..
SN65LVDS95DGGG4 ,Serdes (Serializer/Deserializer) Transmitter 48-TSSOP -40 to 85This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated cir ..
SN65LVDS95DGGR ,Serdes (Serializer/Deserializer) TransmitterBLOCK DIAGRAMParallel-Load 7-BitShift Register7Y0PD0–6 A,B, ...GY0MSerial/LOADCLKParallel-Load 7-Bi ..
SN65LVDS95DGGRG4 ,Serdes (Serializer/Deserializer) Transmitter 48-TSSOP -40 to 85FEATURESDGG PACKAGE• 3:21 Data Channel Compression at up to(TOP VIEW)1.428 Gigabits/s ThroughputD4 ..
SN65LVDS95DGGRG4 ,Serdes (Serializer/Deserializer) Transmitter 48-TSSOP -40 to 85 SLLS297J–MAY 1998–REVISED MAY 2011DnCLKIN’LVDS95CLKOUTPrevious Cycle Current Cycle NextY0 D6 D5 D4 ..
SN74HCT08DR ,Quadruple 2-Input Positive-AND GatesSN54HCT08, SN74HCT08QUADRUPLE 2-INPUT POSITIVE-AND GATESSCLS063D – NOVEMBER 1988 – REVISED AUIGUST ..
SN74HCT08N ,Quadruple 2-Input Positive-AND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HCT08NSR ,Quadruple 2-Input Positive-AND Gatesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74HCT08PW ,Quadruple 2-Input Positive-AND Gateslogic diagram (positive logic)AYB†absolute
SN74HCT08PW ,Quadruple 2-Input Positive-AND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HCT08PWR ,Quadruple 2-Input Positive-AND GatesSN54HCT08, SN74HCT08QUADRUPLE 2-INPUT POSITIVE-AND GATESSCLS063D – NOVEMBER 1988 – REVISED AUIGUST ..
SN65LVDS94-SN65LVDS94DGG-SN65LVDS94DGGG4-SN65LVDS94DGGR-SN65LVDS94DGGRG4
Serdes (Serializer/Deserializer) Receiver
FEATURESLVDSGND
LVDSVCC
LVDSGND
CLKINM
LVDSGND
PLLGND
PLLGND
CLKOUT
VCC
D21
D20
D19
GND
D18
D17
D16
VCC
D15
D14
D13
GND
D12
D11
D10
VCC
GND
VCC
DGG PACKAGE
(TOP VIEW)
DESCRIPTION
LVDS SERDES RECEIVER 4:28 Data Channel Expansionat upto 1.904
Gigabits per Second Throughput Suited for Point-to-Point Subsystem
Communication With Very EMI 4 Data Channels and Clock
Differential Channelsin and Data and
Clock Out Low-Voltage TTL Out Operates Froma Single 3.3-V Supply and
250 mW (Typ) 5-V Tolerant SHTDN Input Rising Clock Edge Triggered Outputs Bus Pins Tolerate 4-kV HBM Packagedin Thin Shrink Small-Outline
Package With20 Mil Terminal Pitch Consumes<1 mW When Disabled Wide Phase-Lock Input Frequency Range MHzto68 MHz No External Components Required for PLL Meetsor Exceeds the Requirementsof ANSI
EIA/TIA-644 Standard Industrial Temperature Qualified= -40°Cto 85°C Replacement for the DS90CR286The SN65LVDS94 LVDS serdes receiver contains serial-in 7-bit parallel-out shift and five low-voltage differential signaling (LVDS) line receiversina single
integrated circuit. These functions receiptof synchronous data from transmitter, such as the and SN65LVDS95, five balanced-pair conductors andto 28 bitsof single-ended synchronous dataata lower transfer rate. the high-speed datais received and loaded intoat the rate seven times the input clockis then unloadedtoa 28-bit wide LVTTL parallel busat the CLKIN rate.A
