SN65LVDS86AQDGGRQ1 ,Automotive Catalog FlatLink Receiver 48-TSSOP -40 to 125 SLLS768A–AUGUST 2006–REVISED JANUARY 2012ÇÇÉÉÇÇÇÉÉÇÇÇÇÉÉÇÇÇÉÉÇÇCLKINÇÇÉÉÇÇÇÉÉÇÇPrevious Cycle Curr ..
SN65LVDS93ADGGR ,10MHzFeatures 2 Applications1• Industrial Temperature Range –40°C to 85°C • LCD Display Panel Drivers• L ..
SN65LVDS93DGG ,Serdes (Serializer/Deserializer) TransmitterFEATURESeach loaded into registers upon the edge of the input• 28:4 Data Channel Compression at up ..
SN65LVDS93DGGR ,Serdes (Serializer/Deserializer) Transmitter........ SLLS302G–MAY 1998–REVISED MAY 2009ÉÉÉÉÉÉÉÉÉÉÉÉÉÉD0ÉÉÉÉÉÉÉÉÉÉÉÉÉÉCLKINorÉÉÇÇÇÉÉÇÇCLKINÉÉÇÇÇ ..
SN65LVDS93DGGRG4 ,Serdes (Serializer/Deserializer) Transmitter 56-TSSOP -40 to 85These devices have limited built-in ESD protection. The leads should be shorted together or the dev ..
SN65LVDS94 ,Serdes (Serializer/Deserializer) ReceiverSLLS298F–MAY 1998–REVISED JANUARY 2006These devices have limited built-in ESD protection. The leads ..
SN74HCT08D ,Quadruple 2-Input Positive-AND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HCT08DBLE ,Quadruple 2-Input Positive-AND GatesSN54HCT08, SN74HCT08QUADRUPLE 2-INPUT POSITIVE-AND GATESSCLS063D – NOVEMBER 1988 – REVISED AUIGUST ..
SN74HCT08DBR ,Quadruple 2-Input Positive-AND Gateslogic diagram (positive logic)AYB†absolute
SN74HCT08DR ,Quadruple 2-Input Positive-AND GatesSN54HCT08, SN74HCT08QUADRUPLE 2-INPUT POSITIVE-AND GATESSCLS063D – NOVEMBER 1988 – REVISED AUIGUST ..
SN74HCT08N ,Quadruple 2-Input Positive-AND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HCT08NSR ,Quadruple 2-Input Positive-AND Gatesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN65LVDS86AQDGGRG4-SN65LVDS86AQDGGRQ1
Automotive Catalog FlatLink Receiver 48-TSSOP -40 to 125
D17
D18
D19
D20
LVDSGND
A0M
A0P
A1M
A1P
LVDSVCC
LVDSGND
A2M
A2P
CLKINM
CLKINP
LVDSGND
PLLGND
PLLVCC
PLLGND
SHTDN
CLKOUT
NC − Not connected
SN65LVDS86A-Q1 Suited for SVGA, XGA,or SXGA Display Data
Transmission From Controllerto Display With
Very Low Three Data Channels and Clock Low-Voltage
Differential ChannelsIn and 21 Data and Clock
Low-Voltage TTL Channels Out Operates Froma Single 3.3-V Supply Tolerates 4-kV Human-Body Model (HBM) ESD Packagedin Thin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal Pitch Consumes Less Than1 mW When Disabled Wide Phase-Lock Input Frequency Range MHzto68 MHz No External Components Required for PLL Inputs Meetor Exceed the Standard
Requirementsof ANSI EIA/TIA-644 Standard Improved Replacement for the SN75LVDS86
and NSC DS90C364 Improved Jitter Tolerance Qualified for Automotive Applications receiver contains three serial-in 7-bit parallel-out shift and four (LVDS) line receiversina single integrated circuit. These functions receipt such '83, '84, over four bitsof single-ended LVTTL synchronous dataata datais received and loaded into registers
clock (CLKIN) rate. unloadedtoa 21-bit wide LVTTL parallelat theon the falling edgeof the output clock (CLKOUT). line-termination resistors for the differential and littleat the inputto the transmitter and output The only user interventionis the the shutdown/clear clock and shut off the LVDS receivers for lower power consumption.A low registerstoa low level.
