SN65LVDS302ZQER ,Programmable 27-Bit Display Serial Interface Receiver 80-BGA MICROSTAR JUNIOR -40 to 85Features 2 Applications1• Serial Interface Technology • Small Low-Emission Interface between Graphi ..
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SN74HCT00D ,Quadruple 2-Input Positive-NAND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HCT00DBR ,Quadruple 2-Input Positive-NAND Gates 14-SSOP -40 to 85maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
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SN74HCT00NSR ,Quadruple 2-Input Positive-NAND GatesSN54HCT00, SN74HCT00QUADRUPLE 2-INPUT POSITIVE-NAND GATESSCLS062D – NOVEMBER 1988 – REVISED AUGUST ..
SN65LVDS302ZQER
Programmable 27-Bit Display Serial Interface Receiver
Application
Processor
with CMOS
Video Interface
LVDS301
LVDS311
LVDS302
LVDS314
LCD
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
SN65LVDS302SLLS733D–JUNE 2006–REVISED MAY 2016
SN65LVDS302 Programmable 27-Bit Serial-to-Parallel Receiver Features Serial Interface Technology Compatible With FlatLink™3G suchas
SN65LVDS301 Supports Video Interfacesupto 24-bit RGB Data
and3 Control Bits Received over1,2or3
SubLVDS Differential Lines SubLVDS Differential Voltage Levels Upto 1.755-Gbps Data Throughput Three Operating Modesto Conserve Power Active mode QVGA:17 mW Typical Shutdown: 0.7 μW Typical Standby Mode:27 μW Typical Bus-Swap Function for PCB-Layout Flexibility ESD Rating>4 kV (HBM) Pixel Clock Rangeof4 MHzto 65 MHz Failsafe onall CMOS Inputs Packagedin 5-mm× 5-mm MicroStar Junior
μBGA® With 0.5-mm Ball Pitch Very low EMI meets SAE J1752/3 'Kh'-spec
Applications Small Low-Emission Interface between
Controller and LCD Display Cameras, Camcorders, Embedded Portable Multimedia Players
DescriptionThe SN65LVDS302 receiver
FlatLink™3G compliant serial input
data outputs. The SN65LVDS302
one shift registerto load 30 bits from
inputs and latches the 24 pixel bits
outto the parallel CMOS outputs after
parity bit.If the parity check confirms
the Channel Parity Error (CPE) output parity erroris detected, the CPE output
high pulse while the data output bus
newly-received pixel. Instead, the
held on the output bus for another clock
Device Information(1) Forall available packages, see the orderable
the endofthe data sheet.
Implementation Example
