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|SN65LVDS152 from TI, Texas Instruments 62pcs , TSSOP,MuxIt (TM) Receiver-Deserializer|
FEATURESSN65LVDS152DA2• A Member of the MuxIt™ Serializer-(Marked as 65LVDS152)Deserializer Building-Block Chip Family(TOP VIEW)• Supports Deserialization of One Serial LinkDI+ V1 32CCData Channel Input at Rates up to 200 MbpsDI– 2 LVI31• PLL Lock/Valid Input Provided to EnableGND 3 MCI–30Parallel Data and Clock OutputsLCI+ 4 29 MCI+• Cascadable With Additional SN65LVDS152LCI– 5 GND28MuxIt Receiver-Deserializers for Wider ParallelGND 6 DCO27Output Data Channel Widths7CO_EN 26 DO–9• LVDS Compatible Differential Inputs andV 8 25 DO–8CCOutputs Meet or Exceed the Requirements ofGND 9 24 DO–7ANSI TIA/EIA-644-A10V 23 DO–6CC• LVDS Input and Output ESD Protection11V 22 DO–5CCExceeds 12 kV HBMGND 12 21 DO–4• LVTTL Compatible Inputs for Lock/Valid and13GND 20 DO–3Enables Are 5-V Tolerant14EN 19 DO–215• Operates With 3.3-V Supply 18CO– DO–116 17CO+ DO–0• Packaged in 32-Pin DA Thin ShrinkSmall-Outline Package With 26-Mil TerminalPitchDESCRIPTIONMuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers anddeserializers. The system allows for wide parallel data to be transmitted through a reduced number oftransmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or LVCMOS)data interface. The number of bits multiplexed per transmission line is user selectable, allowing for highertransmission efficiencies than with other existing fixed ratio solutions. MuxIt utilizes the LVDS (TIA/EIA-644-A)low voltage differential signaling technology for communications between the data source and data destination.The MuxIt family initially includes three devices supporting simplex communications: the SN65LVDS150 phaselocked loop frequency multiplier, the SN65LVDS151 serializer-transmitter, and the SN65LVDS152receiver-deserializer.The SN65LVDS152 consists of three LVDS differential transmission line receivers, an LVDS differentialtransmission line driver, a 10-bit serial-in/parallel-out shift register, plus associated input and output buffers. Itreceives serialized data over an LVDS transmission line link, deserializes (demultiplexes) it, and delivers it onparallel data outputs, DO–0 through DO–9. Data received over the link is clocked at a factor of M times theoriginal parallel data frequency. The multiplexing ratio M, or number of bits per data clock cycle, is programmedwith configuration pins (M1→ M5) on the companion SN65LVDS150 MuxIt programmable PLL frequencymultiplier. Up to 10 bits of data may be deserialized and output by each SN65LVDS152. Two or moreSN65LVDS152 units may be connected in series (cascaded) to accommodate wider parallel data paths forhigher serialization values. The range of multiplexing ratio M supported by the SN65LVDS150 MuxItprogrammable PLL frequency multiplier is between 4 and 40. Table 1 shows some of the combinations of LCIand MCI supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier.1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.2MuxIt is a trademark of Texas Instruments..Copyright 2000–2011, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does not.SN65LVDS152SLLS445A–DECEMBER 2000–REVISED SEPTEMBER 2011
|SN65LVDS176DGK TI |
|SN65LVDS152 ,MuxIt (TM) Receiver-DeserializerFEATURESSN65LVDS152DA2• A Member of the MuxIt™ Serializer-(Marked as 65LVDS152)Deserializer Buildin ..|
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