SN65LVDS152 ,MuxIt (TM) Receiver-DeserializerFEATURESSN65LVDS152DA2• A Member of the MuxIt™ Serializer-(Marked as 65LVDS152)Deserializer Buildin ..
SN65LVDS179D ,Single Full-Duplex LVDS TransceiverBlock Diagram. 173 Description....... 110.3 Feature Description.. 174 Revision History........ 210. ..
SN65LVDS179DG4 ,Single Full-Duplex LVDS Transceiver 8-SOIC -40 to 85Maximum Ratings . 613 Layout.... 288.2 ESD Ratings........ 613.1 Layout Guidelines.... 288.3 Recomm ..
SN65LVDS179DGK ,Single Full-Duplex LVDS TransceiverFeatures 3 DescriptionThe SN65LVDS179, SN65LVDS180, SN65LVDS050,1• Meets or Exceeds the Requirement ..
SN65LVDS179DGKR ,Single Full-Duplex LVDS TransceiverSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN65LVDS179,SN65LVDS ..
SN65LVDS179DGKR ,Single Full-Duplex LVDS TransceiverElectrical Characteristics ........ 814.3 Related Links.. 328.8 Driver Switching Characteristics... ..
SN74HC74NSR ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetMaximum Ratings.. 411.1 Layout Guidelines.... 136.2 ESD Ratings ...... 411.2 Layout Example....... ..
SN74HC74PW ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN54HC74,SN74HC74SCL ..
SN74HC74PWR ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN54HC74,SN74HC74SCL ..
SN74HC74PWRG4 ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-TSSOP -40 to 85Sample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN54HC74,SN74HC74SCL ..
SN74HC74QPWRG4Q1 ,Automotive Catalog Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-TSSOP -40 to 125SN74HC74-Q1DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPWITH CLEAR AND PRESETSCLS577A − MARCH 2004 ..
SN74HC74QPWRQ1 ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Presetmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN65LVDS152
MuxIt (TM) Receiver-Deserializer
SN65LVDS152DA
(Marked as 65LVDS152)
(TOP VIEW)VCC
LVI
MCI–
MCI+
GND
DCO
DO–9
DO–8
DO–7
DO–6
DO–5
DO–4
DO–3
DO–2
DO–1
DO–0
1FEATURES A Memberof the MuxIt™ Serializer-
Deserializer Building-Block Chip Family Supports Deserializationof One Serial Link
Data Channel Inputat Rates upto 200 Mbps PLL Lock/Valid Input Providedto Enable
Parallel Data and Clock Outputs Cascadable With Additional SN65LVDS152
MuxIt Receiver-Deserializers for Wider Parallel
Output Data Channel Widths LVDS Compatible Differential Inputs and
Outputs Meetor Exceed the Requirementsof
ANSI TIA/EIA-644-A LVDS Input and Output ESD Protection
Exceeds12 kV HBM LVTTL Compatible Inputs for Lock/Valid and
Enables Are 5-V Tolerant Operates With 3.3-V Supply Packagedin 32-Pin DA Thin Shrink
Small-Outline Package With 26-Mil Terminal
Pitch
DESCRIPTIONMuxItisa familyof general-purpose, multiple-chip building blocks parallel data serializers and
deserializers. The system allows for wide parallel datato be througha reduced number of
transmission lines over distances greater than can be achieved with (e.g., LVTTLor LVCMOS)
data interface. The numberof bits multiplexed per transmission user selectable, allowing for higher
transmission efficiencies than with other existing fixed ratio solutions. utilizes the LVDS (TIA/EIA-644-A)
low voltage differential signaling technologyfor communications between data source and data destination. includes three devices supporting the SN65LVDS150 phase the SN65LVDS151 and the SN65LVDS152 differential an LVDS differential shift input and output buffers.It line link,it, DO–9. Data receivedofM times the multiplexing ratioM,or data cycle,
with configuration on the companion SN65LVDS150 MuxIt frequency may be deserialized and output each SN65LVDS152. orin series (cascaded)to parallel for range of multiplexing ratiois between4 and 40. Tableof LCI MuxIt programmable PLL multiplier.
