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SN65LVDS151 from TI, Texas Instruments 64pcs , TSSOP,MuxIt (TM) Serializer-Transmitter
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SN65LVDS151 TI N/a 64

SLLS444A–DECEMBER 2000These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.DESCRIPTION (CONTINUED)Data is parallel loaded into the SN65LVDS151 input latches on the first rising edge of the M-clock input (MCI)signal following a rising edge of the link clock reference input (LCRI). The data is read out serially from theSN65LVDS151 shift registers on the rising edges of the M-clock input (MCI). The lowest order bit of parallel inputdata, DI-0, is output from DO on the third rising edge of MCI following the rising edge of LCRI. The remaining bitsof parallel input data, DI-1 → DI-(M-1) are clocked out sequentially, in ascending order, by subsequent MCI risingedges. The link clock output (LCO) signal rising edge is synchronized to the data output (DO) by an internalcircuit clocked by MCI. The LCO signal rising edge follows the first rising edge of MCI after the rising edge ofLCRI. Examples of operating waveforms for values of M = 4 and M = 10 are provided in Table 1.Both the LCRI and MCI signals are intended to be sourced from the SN65LVDS150 MuxIt programmablefrequency multiplier. They are carried over LVDS differential connections to minimize skew and jitter. TheSN65LVDS151 includes LVDS differential line drivers for both the serialized data output (DO) stream and the linkclock output (LCO). The cascade input (CI) is also an LVDS connection, and when it is used it is tied to the DOoutput of the preceding SN65LVDS151.An internal power-on reset (POR) and an enable input (EN) control the operation of the SN65LVDS151. WhenV is below 1.5 V, or when EN is low, the device is in a low-power disabled state, and the DO and LCOCCdifferential outputs are in a high-impedance state. When V is above 3 V and EN is high, the device and the twoCCdifferential outputs are enabled and operating to specifications. The link clock output enable input (LCO_EN) isused to turn off the LCO output when it is not being used. Cascade input enable (CI_EN) is used to turn off theCI input when it is not being used.Serialized data bits are output from the DO output, starting in ascending order, from parallel input bit DI-0. Thenumber of serialized data bits output per data clock cycle is determined by the multiplexing ratio M. For values ofM less than or equal to 10, the cascade input (CI±) is not used, and only the first M parallel input bits (DI-0thought DI-[M-1]) are used. For values of M greater than 10, all ten parallel input bits (DI-0 though DI-9) areused, and the cascade input is used to shift in the remaining data bits from additional SN65LVDS151 serializers.Table 2 shows which input data bits are used as a function of the multiplier M.Table 1. Example Combinations of LCRI and MCI Supported by theSN65LVDS150 Muxit Programmable PLL Frequency MultiplierLCRI, MHz MCI, MHzM MINIMUM MAXIMUM MINIMUM MAXIMUM4 5 50 20 20010 5 20 50 20020 5 10 100 20040 5 5 200 2002Submit Documentation FeedbackSN65LVDS151

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