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Partno	Mfg	Dc	Qty	Available	Descript
SN65LVDS117DGG	TI	N/a	150	avai	Dual 8-Port LVDS Repeater
SN65LVDS117DGGR	TI	N/a	2297	avai	Dual 8-Port LVDS Repeater

SN65LVDS117DGGR ,Dual 8-Port LVDS RepeaterFEATURESLVDS signaling technique, is for point-to-point or• Two Line Receivers and Eight ('109) orp ..
SN65LVDS122D ,2X2 1.5 Gbps LVDS Crosspoint SwitchELECTRICAL CHARACTERISTICSover recommended operating conditions (unless otherwise noted)(1)PARAMETE ..
SN65LVDS122DR ,2X2 1.5 Gbps LVDS Crosspoint SwitchELECTRICAL CHARACTERISTICSover recommended operating conditions (unless otherwise noted)(1)PARAMETE ..
SN65LVDS122PW ,2X2 1.5 Gbps LVDS Crosspoint SwitchFEATURES DESCRIPTION(1)• Designed for Signaling Rates Up ToThe SN65LVDS122 and SN65LVDT122 are1.5 G ..
SN65LVDS122PWR ,2X2 1.5 Gbps LVDS Crosspoint SwitchMAXIMUM RATINGS(1)over operating free-air temperature range unless otherwise notedSN65LVDS122, SN65 ..
SN65LVDS122PWRG4 ,2X2 1.5 Gbps LVDS Crosspoint Switch 16-TSSOP -40 to 85maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
SN74HC74DR ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetLogic Diagram (Positive Logic)PRECCLKCQC TGCCCCTGD TGTGQCCCCLR1An IMPORTANT NOTICE at the end of th ..
SN74HC74DRG4 ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SOIC -40 to 85Logic Diagram (Positive Logic)PRECCLKCQC TGCCCCTGD TGTGQCCCCLR1An IMPORTANT NOTICE at the end of th ..
SN74HC74MPWREP ,Enhanced Product Dual D-Type Positive Edge Triggered Flip Flop With Clear And Preset 14-TSSOP -55 to 125FEATURES• Controlled Baseline • Wide Operating Voltage Range of 2 V to 6 V– One Assembly Site • Out ..
SN74HC74N ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetMaximum Ratings.. 411.1 Layout Guidelines.... 136.2 ESD Ratings ...... 411.2 Layout Example....... ..
SN74HC74NSR ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetMaximum Ratings.. 411.1 Layout Guidelines.... 136.2 ESD Ratings ...... 411.2 Layout Example....... ..
SN74HC74PW ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN54HC74,SN74HC74SCL ..

SN65LVDS117DGG-SN65LVDS117DGGR
Dual 8-Port LVDS Repeater
FEATURES
DESCRIPTION
GND
VCC
VCC
GND
ENM
ENA
ENB
ENC
END
GND
GND
VCC
VCC
GND
GND
ENE
ENF
ENG
ENH
GND
A1Y
A1Z
A2Y
A2Z
B1Y
B1Z
B2Y
B2Z
C1Y
C1Z
C2Y
C2Z
D1Y
D1Z
D2Y
D2Z
E1Y
E1Z
E2Y
E2Z
F1Y
F1Z
F2Y
F2Z
G1Y
G1Z
G2Y
H2Z
SN65LVDS117
DGG PACKAGE
(TOP VIEW)
GND
VCC
GND
ENM
ENA
ENB
GND
ENC
END
GND
VCC
GND
A1Y
A1Z
A2Y
A2Z
B1Y
B1Z
B2Y
B2Z
C1Y
C1Z
C2Y
C2Z
D1Y
D1Z
D2Y
D2Z
SN65LVDS109
DBT PACKAGE
(TOP VIEW)
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS
The intended applicationof these devices, and the
LVDS signaling technique,is for point-to-point or• Two Line Receivers and Eight ('109)or point-to-multipoint (distributed simplex) basebandSixteen ('117) Line Drivers Meetor Exceed the data transmission on controlled impedance mediaofRequirementsof ANSI EIA/TIA-644 Standard approximately 100 Ω. The transmission media may• Typical Data Signaling Ratesto 400 Mbpsor be printed-circuit board traces, backplanes,or cables.
Clock Frequenciesto 400 MHz The large numberof drivers integrated into the same
silicon substrate, along with the low pulse skewof• Outputs Arrangedin Pairs From Each Bank balanced signaling, provides extremely precise timing• Enabling Logic Allows Individual Controlof alignment of the signals being repeated from theEach Driver Output Pair, Plus All Outputs inputs. This is particularly advantageous for im- Low-Voltage Differential Signaling With plementing system clock and data distribution trees.
Typical Output Voltageof 350 mV anda 100-Ω The SN65LVDS109 and SN65LVDS117 areLoad characterizedfor operation from –40°Cto 85°C.• Electrically Compatible With LVDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL,or HSTL Outputs With External
Termination Networks Propagation Delay Times< 4.5 ns Output Skew Less Than 550 ps Bank Skew
Less Than150 ps Part-to-Part Skew Less Than
1.5 ns Total Power Dissipation Typically <500 mW
With All Ports Enabled andat 200 MHz Driver Outputsor Receiver Input Equals High
Impedance When Disabledor With VCC< 1.5V Bus-Pin ESD Protection Exceeds12 kV Packagedin Thin Shrink Small-Outline
Package With 20-Mil Terminal Pitch
The SN65LVDS109 and SN65LVDS117 are con-
figuredas two identical banks, each bank having one
differential line receiver connected to either four
('109) or eight ('117) differential line drivers. The
outputs are arrangedin pairs having one output from
eachof the two banks. Individual output enables are
provided for each pairof outputs and an additionalis provided forall outputs. and line drivers implement the of low-voltage differential (LVDS). specifiedin EIA/TIA-644,
ation characteristicsof the media, the noise coupling

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