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Partno	Mfg	Dc	Qty	Available	Descript
SN65LVDS116DGG	TI	N/a	2163	avai	1:16 LVDS Clock Fanout Buffer
SN65LVDS116DGGR	TI	N/a	4552	avai	1:16 LVDS Clock Fanout Buffer

SN65LVDS116DGGR ,1:16 LVDS Clock Fanout BufferSLLS370D–SEPTEMBER 1999–REVISED FEBRUARY 2005(1)FUNCTION TABLEINPUT OUTPUTV = V – V SM EN EN S1 S0 ..
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SN65LVDS122PW ,2X2 1.5 Gbps LVDS Crosspoint SwitchFEATURES DESCRIPTION(1)• Designed for Signaling Rates Up ToThe SN65LVDS122 and SN65LVDT122 are1.5 G ..
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SN74HC74DR ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetLogic Diagram (Positive Logic)PRECCLKCQC TGCCCCTGD TGTGQCCCCLR1An IMPORTANT NOTICE at the end of th ..
SN74HC74DRG4 ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SOIC -40 to 85Logic Diagram (Positive Logic)PRECCLKCQC TGCCCCTGD TGTGQCCCCLR1An IMPORTANT NOTICE at the end of th ..
SN74HC74MPWREP ,Enhanced Product Dual D-Type Positive Edge Triggered Flip Flop With Clear And Preset 14-TSSOP -55 to 125FEATURES• Controlled Baseline • Wide Operating Voltage Range of 2 V to 6 V– One Assembly Site • Out ..
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SN65LVDS116DGG-SN65LVDS116DGGR
1:16 LVDS Clock Fanout Buffer
FEATURES
DESCRIPTION
GND
VCC
VCC
GND
ENA
ENA
ENB
ENB
GND
VCC
VCC
GND
ENC
ENC
END
END
GND
VCC
A1Y
A1Z
A2Y
A2Z
A3Y
A3Z
A4Y
A4Z
B1Y
B1Z
B2Y
B2Z
B3Y
B3Z
B4Y
B4Z
C1Y
C1Z
C2Y
C2Z
C3Y
C3Z
C4Y
C4Z
D1Y
D1Z
D2Y
D2Z
D3Y
D3Z
DGG PACKAGE
(TOP VIEW)
16-PORT LVDS REPEATER
The intended applicationof this device and signaling
techniqueis for point-to-pointor multidrop baseband• One Receiver and Sixteen Line Drivers Meet data transmission over controlled impedance mediaor Exceed the Requirementsof ANSI of approximately 100Ω. The transmission media mayEIA/TIA-644 Standard be printed-circuit board traces, backplanes,or cables.• Typical Signaling Ratesto 400 Mbpsor The large numberof drivers integrated into the same
Clockto 400 MHz substrate along with the low pulse skewof balanced
signaling, allows extremely precise timing alignment• Enabling Logic Allows Separate Controlof of the signals repeated from the input. This isEach Bankof Four Channelsor 2-Bit particularly advantageousin system clock distribution.Selectionof Any Oneof the Four Banks
The SN65LVDS116is characterised for operation• Low-Voltage Differential Signaling With from –40°Cto 85°C.Typical Voltageof 350 mV anda 100-Ω
Load Electrically Compatible With LVDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL, HSTL Outputs With External
Termination Networks Propagation Delay Times< 4.7 ns OutputIs< 300ps and Part-to-Part
Skewns Total Power Dissipation Typically 470 mW
With All Enabled andat 200 MHz Driveror Receiver InputIs High
Impedance When Disabledor WithVCC< 1.5 Bus-Pin Protection Exceeds12 kVin Thin Shrink Small-Outline
Package 20-Mil Terminal Pitch
The SN65LVDS116is one differential line receiver
connected sixteen differential line drivers that
implement electrical characteristicsof low-voltage
differential (LVDS). LVDS, as specifiedin
EIA/TIA-644,a data signaling technique that offers
the low-power, low-noise coupling, and fast switching
speedsto dataat relatively long distances. The rate and distanceof data transfer upon the attenuation characteristicsof noise couplingto the environment, and

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