SN65LVDS108DBTRG4 ,1:8 LVDS Clock Fanout Buffer 38-TSSOP -40 to 85FEATURESDBT PACKAGE• One Line Receiver and Eight Line Drivers(TOP VIEW)Configured as an 8-Port LVDS ..
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SN65LVDS109DBTR ,Dual 4-Port LVDS Repeaterelectrical characteristics of low-voltage differential ENH G1Z26 39signaling (LVDS). LVDS, as speci ..
SN65LVDS109DBTRG4 ,Dual 4-Port LVDS Repeater 38-TSSOP -40 to 85SLLS369F–AUGUST 1999–REVISED FEBRUARY 2005SELECTION GUIDE TO LVDS SPLITTERSThe SN65LVDS109 and SN75 ..
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SN65LVDS116DGGR ,1:16 LVDS Clock Fanout BufferSLLS370D–SEPTEMBER 1999–REVISED FEBRUARY 2005(1)FUNCTION TABLEINPUT OUTPUTV = V – V SM EN EN S1 S0 ..
SN74HC74D ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetMaximum Ratings.. 411.1 Layout Guidelines.... 136.2 ESD Ratings ...... 411.2 Layout Example....... ..
SN74HC74DBR ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetElectrical Characteristics....... 512.2 Related Links.. 146.6 Timing Requirements... 612.3 Communit ..
SN74HC74DBR ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetFeatures 3 DescriptionThe SNx4HC74 devices contain two independent D-1• Wide Operating Voltage Rang ..
SN74HC74DR ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetLogic Diagram (Positive Logic)PRECCLKCQC TGCCCCTGD TGTGQCCCCLR1An IMPORTANT NOTICE at the end of th ..
SN74HC74DRG4 ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SOIC -40 to 85Logic Diagram (Positive Logic)PRECCLKCQC TGCCCCTGD TGTGQCCCCLR1An IMPORTANT NOTICE at the end of th ..
SN74HC74MPWREP ,Enhanced Product Dual D-Type Positive Edge Triggered Flip Flop With Clear And Preset 14-TSSOP -55 to 125FEATURES• Controlled Baseline • Wide Operating Voltage Range of 2 V to 6 V– One Assembly Site • Out ..
SN65LVDS108DBT-SN65LVDS108DBTR-SN65LVDS108DBTRG4
1:8 LVDS Clock Fanout Buffer
www.ti.com
FEATURESGND
VCC
GND
ENM
ENA
ENB
ENC
END
ENE
ENF
ENG
ENH
GND
VCC
GND
DBT PACKAGE
(TOP VIEW)NC – No internal connection
DESCRIPTION
SN65LVDS108SLLS399E–NOVEMBER 1999–REVISED FEBRUARY 2005
8-PORT LVDS REPEATER One Line Receiver and Eight Line Drivers
Configuredas an 8-Port LVDS Repeater Line Receiver and Line Drivers Meetor
Exceed the Requirementsof ANSI EIA/TIA-644
Standard Typical Data Signaling Ratesto 400 Mbpsor
Clock Frequenciesto 400 MHz Enabling Logic Allows Individual Controlof
Each Driver Output, Plus All Outputs Low-Voltage Differential Signaling With
Typical Output Voltageof 350 mV anda 100-Ω
Load Electrically Compatible With LVDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL,or HSTL Outputs With External
Termination Networks Propagation Delay Times< 4.7 ns Output Skew Less Than 300 ps and
Part-to-Part Skew Less Than 1.5ns Total Power Dissipationat 200 MHz Typically
Less Than 330 mW With8 Channels Enabled Driver Outputsor Receiver Input Equals High
Impedance When Disabledor With VCC< 1.5V Bus-Pin ESD Protection Exceeds12 kV Packagedin Thin Shrink Small-Outline
Package With 20-Mil Terminal PitchThe SN65LVDS108is configured as one differential line receiver connectedto eight differential line drivers.
Individual output enables are provided for each output andan additional enableis providedforall outputs.
The line receivers and line drivers implement the electrical characteristicsof low-voltage differential signaling
(LVDS). LVDS, as specifiedin EIA/TIA-644,isa data signaling technique that offers low power, low noise
emission, high noise immunity, and high switching speeds. (Note: The ultimate rate and distanceof data transfer dependent upon the attenuation characteristicsof the media, the noise couplingto the environment, and other
system characteristics.)
The intended application of this device, and the LVDS signaling technique, is for point-to-point or
point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of
approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes,or cables. The
large numberof drivers integrated into the same silicon substrate, along with the low pulse skewof balanced
signaling, provides extremely precise timing alignmentof the signals being repeated from the inputs. Thisis
particularly advantageousfor implementing system clockor data distribution trees.
The SN65LVDS108is characterizedfor operation from –40°Cto 85°C.
