SN65LVDS104PWRG4 ,1:4 LVDS Clock Fanout Buffer 16-TSSOP -40 to 85Electrical Characteristics........ 613.1 Related Links.. 327.8 SN65LVDS104 Switching Characteristic ..
SN65LVDS1050PW ,2.7V Dual LVDS Transmitter/ReceiverFEATURES14SN65LVDS1050PW151Y(Marked as DL1050 or LDS1050)· Typically Meets or Exceeds ANSI1D 13(TOP ..
SN65LVDS1050PWR ,2.7V Dual LVDS Transmitter/Receivermaximum ratings" may cause permanent damage to the device. These are stressratings only, and functi ..
SN65LVDS105D ,1 LVTTL:4 LVDS Clock Fanout Buffer SLLS396G–SEPTEMBER 1999–REVISED DECEMBER 20155 Selection Guide to LVDS RepeatersDEVICE NO. INPUTS ..
SN65LVDS105DR ,1 LVTTL:4 LVDS Clock Fanout BufferFeatures 3 DescriptionThe SN65LVDS10x are a differential line receiver and1• Receiver and Drivers M ..
SN65LVDS105PW ,1 LVTTL:4 LVDS Clock Fanout BufferElectrical Characteristics........ 613.1 Related Links.. 327.8 SN65LVDS104 Switching Characteristic ..
SN74HC74ADBLE ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetLogic Diagram (Positive Logic)PRECCLKCQC TGCCCCTGD TGTGQCCCCLR1An IMPORTANT NOTICE at the end of th ..
SN74HC74D ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetMaximum Ratings.. 411.1 Layout Guidelines.... 136.2 ESD Ratings ...... 411.2 Layout Example....... ..
SN74HC74DBR ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetElectrical Characteristics....... 512.2 Related Links.. 146.6 Timing Requirements... 612.3 Communit ..
SN74HC74DBR ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetFeatures 3 DescriptionThe SNx4HC74 devices contain two independent D-1• Wide Operating Voltage Rang ..
SN74HC74DR ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetLogic Diagram (Positive Logic)PRECCLKCQC TGCCCCTGD TGTGQCCCCLR1An IMPORTANT NOTICE at the end of th ..
SN74HC74DRG4 ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SOIC -40 to 85Logic Diagram (Positive Logic)PRECCLKCQC TGCCCCTGD TGTGQCCCCLR1An IMPORTANT NOTICE at the end of th ..
SN65LVDS104D-SN65LVDS104DRG4-SN65LVDS104PW-SN65LVDS104PWR-SN65LVDS104PWRG4
1:4 LVDS Clock Fanout Buffer
EN1
EN2Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
SN65LVDS104, SN65LVDS105SLLS396G –SEPTEMBER 1999–REVISED DECEMBER 2015
SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters Features 3 DescriptionThe SN65LVDS10x area differential line receiver and Receiver and Drivers Meetor Exceed the a LVTTL input (respectively) connected to fourRequirementsof ANSI EIA/TIA-644 Standard differential line drivers that implement the electrical– SN65LVDS105 Receives Low-Voltage TTL characteristics of low-voltage differential signaling(LVTTL) Levels (LVDS). LVDS,as specifiedin EIA/TIA-644isa data
signaling technique that offers low-power, low-noise– SN65LVDS104 Receives Differential Input
coupling, and switching speedsto transmit dataatLevels, ±100 mV relatively long distances. (Note: The ultimate rate and• Typical Data Signaling Ratesto 400 Mbpsor distance of data transferis dependent upon theClock Frequenciesto 400 MHz attenuation characteristicsof the media, the noise• Operates Froma Single 3.3-V Supply coupling to the environment, and other system
characteristics.)• Low-Voltage Differential Signaling With Typical
Output Voltageof 350 mV anda 100-Ω Load The intended applicationof this device and signaling Propagation Delay Time technique is for point-to-point baseband data
transmission over controlled impedance media of– SN65LVDS105– 2.2ns (Typ) approximately 100 Ω. The transmission media may– SN65LVDS104– 3.1ns (Typ) be printed-circuit board traces, backplanes,or cables. LVTTL Levels Are 5-V Tolerant• Electrically Compatible WithLVPECL, LVTTL, LVCMOS,SSTL,or HSTL Outputs• Driver Outputs Are High-ImpedanceDisabledor With VCC <1.5• Bus-Pin ESD Protection• SOIC and TSSOP Packaging
2 Applications Clock Distribution• Wireless Base Stations• Network Routers
SN65LVDS105 Logic Diagram (Positive Logic)SN65LVDS104 Logic Diagram (Positive Logic)
