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SN65LVDS104PWR from TEXAS, 1810pcs , SSOP,1:4 LVDS Clock Fanout Buffer
Partno Mfg Dc Qty Available
SN65LVDS104PWR TEXAS N/a 1810
SN65LVDS104PWR from TI, Texas Instruments 1726pcs , TSSOP,1:4 LVDS Clock Fanout Buffer

SLLS396G–SEPTEMBER 1999–REVISED DECEMBER 20155 Selection Guide to LVDS RepeatersDEVICE NO. INPUTS NO. OUTPUTS PACKAGE COMMENTSN65LVDS22 2 LVDS 2 LVDS 16-pin D Dual multiplexed LVDS repeaterSN65LVDS104 1 LVDS 4 LVDS 16-pin D 4-Port LVDS repeaterSN65LVDS105 1 LVTTL 4 LVDS 16-pin D 4-Port TTL-to-LVDS repeaterSN65LVDS108 1 LVDS 8 LVDS 38-pin DBT 8-Port LVDS repeaterSN65LVDS109 2 LVDS 8 LVDS 38-pin DBT Dual 4-port LVDS repeaterSN65LVDS116 1 LVDS 16 LVDS 64-pin DGG 16-Port LVDS repeaterSN65LVDS117 2 LVDS 16 LVDS 64-pin DGG Dual 8-port LVDS repeater6 Pin Configuration and FunctionsSN65LVDS104 D or PW PackageSN65LVDS105 D or PW Package16-Pin SOIC or TSSOP16-Pin SOIC or TSSOPTop ViewTop ViewEN1 1Y1 16EN1 1Y1 16EN2 2 15 1ZEN2 2 15 1ZEN3 3 14 2YEN3 3 14 2YV 2Z4 13CCV 4 13 2ZCCGND 5 12 3YGND 5 12 3YA 6 11 3ZA 6 11 3Z7 10B 4YNC 7 10 4YEN4 8 9 4ZEN4 8 9 4ZPin FunctionsPINI/O DESCRIPTIONNAME SN65LVDS104 SN65LVDS105A 6 6 I LVDS input, positive (LVDS104) or LVTTL input, (LVDS105)B 7 — I LVDS input, negativeEN1 1 1 I Enable, channel 1EN2 2 2 I Enable, channel 2EN3 3 3 I Enable, channel 3EN4 8 8 I Enable, channel 4GND 5 5 — GroundNC — 7 — No connectV 4 4 — Supply voltageCC1Y 16 16 O LVDS output, positive, channel 11Z 15 15 O LVDS output, negative, channel 12Y 14 14 O LVDS output, positive, channel 22Z 13 13 O LVDS output, negative, channel 23Y 12 12 O LVDS output, positive, channel 33Z 11 11 O LVDS output, negative, channel 34Y 10 10 O LVDS output, positive, channel 44Z 9 9 O LVDS output, negative, channel 4Copyright 1999–2015, Texas Instruments Incorporated Submit Documentation Feedback 3Product Folder Links: SN65LVDS104 SN65LVDS105SN65LVDS104,SN65LVDS105SLLS396G–SEPTEMBER 1999–REVISED DECEMBER 2015 Logic Diagram (Positive Logic)1Y 1Y1Z 1ZEN1 EN1EN2 EN22Y 2Y2Z2ZEN3EN33Y3YA 3Z3ZAB4Y4Y4Z4ZEN4EN41An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.SN65LVDS104,SN65LVDS105SLLS396G–SEPTEMBER 1999–REVISED DECEMBER 2015

SN65LVDS104PWR ,1:4 LVDS Clock Fanout BufferLogic Diagram (Positive Logic)1Y 1Y1Z 1ZEN1 EN1EN2 EN22Y 2Y2Z2ZEN3EN33Y3YA 3Z3ZAB4Y4Y4Z4ZEN4EN41An ..
SN65LVDS104PWRG4 ,1:4 LVDS Clock Fanout Buffer 16-TSSOP -40 to 85Electrical Characteristics........ 613.1 Related Links.. 327.8 SN65LVDS104 Switching Characteristic ..
SN65LVDS1050PW ,2.7V Dual LVDS Transmitter/ReceiverFEATURES14SN65LVDS1050PW151Y(Marked as DL1050 or LDS1050)· Typically Meets or Exceeds ANSI1D 13(TOP ..
SN65LVDS1050PWR ,2.7V Dual LVDS Transmitter/Receivermaximum ratings" may cause permanent damage to the device. These are stressratings only, and functi ..
SN65LVDS105D ,1 LVTTL:4 LVDS Clock Fanout Buffer SLLS396G–SEPTEMBER 1999–REVISED DECEMBER 20155 Selection Guide to LVDS RepeatersDEVICE NO. INPUTS ..
SN74HC74 ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV S ..
SN74HC74ADBLE ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetLogic Diagram (Positive Logic)PRECCLKCQC TGCCCCTGD TGTGQCCCCLR1An IMPORTANT NOTICE at the end of th ..
SN74HC74D ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and PresetMaximum Ratings.. 411.1 Layout Guidelines.... 136.2 ESD Ratings ...... 411.2 Layout Example....... ..
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