SN65LVDS100DRG4 ,2 Gbps LVDS/LVPECL/CML to LVDS Repeater/Translator 8-SOIC -40 to 85Features... 110.3 Feature Description.. 152 Applications..... 110.4 Device Functional Modes.. 203 D ..
SN65LVDS101D ,2Gbps LVDS/LVPECL/CML to LVPECL Repeater/TranslatorElectrical Characteristics....... 514.3 Trademarks..... 338.6 Switching Characteristics...... 614.4 ..
SN65LVDS101D ,2Gbps LVDS/LVPECL/CML to LVPECL Repeater/Translator SLLS516E–AUGUST 2002–REVISED JULY 20155 Description (Continued)The outputs of the SN65LVDS100 and ..
SN65LVDS101DG4 ,2Gbps LVDS/LVPECL/CML to LVPECL Repeater/Translator 8-SOIC -40 to 85Sample & Support & ReferenceProduct Tools &TechnicalCommunityBuy DesignFolder Documents SoftwareSN6 ..
SN65LVDS101DGK ,2Gbps LVDS/LVPECL/CML to LVPECL Repeater/TranslatorMaximum Ratingsover operating free-air temperature range unless otherwise notedMIN MAX UNIT(2)V Sup ..
SN65LVDS101DGK ,2Gbps LVDS/LVPECL/CML to LVPECL Repeater/TranslatorFeatures 3 DescriptionThe SN65LVDS100, SN65LVDT100, SN65LVDS101,1• Designed for Signaling Rates≥ 2 ..
SN74HC7002D ,Quadruple Positive-NOR Gates With Schmitt-Trigger Inputs SCLS033F − MARCH 1984 − R ..
SN74HC7032 ,Quadruple Positive-OR Gates With Schmitt-Trigger Inputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HC7032D ,Quadruple Positive-OR Gates With Schmitt-Trigger Inputs SCLS036E − MARCH 1984 − REVI ..
SN74HC7032DR , QUADRUPLE POSITIVE-OR GATES WITH SCHMITT-TRIGGER INPUTS
SN74HC7032N ,Quadruple Positive-OR Gates With Schmitt-Trigger Inputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74HC7032NSR , QUADRUPLE POSITIVE-OR GATES WITH SCHMITT-TRIGGER INPUTS
SN65LVDS100D-SN65LVDS100DGK-SN65LVDS100DGKR-SN65LVDS100DGKRG4-SN65LVDS100DR-SN65LVDS100DRG4
2Gbps LVDS/LVPECL/CML to LVDS Repeater/Translator
FUNCTIONAL DIAGRAM
VCC
SN65LVDS100 and SN65LVDS101
SN65LVDT100 and SN65LVDT101Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
Reference
Design
SN65LVDS100, SN65LVDT100, SN65LVDS101, SN65LVDT101SLLS516E –AUGUST 2002–REVISED JULY 2015
SN65LVDx10x Differential Translator/Repeater Features 3 DescriptionThe SN65LVDS100, SN65LVDT100, SN65LVDS101, Designedfor Signaling Rates≥2 Gbps and SN65LVDT101 are high-speed differential• Total Jitter<65ps receivers and drivers connected as repeaters. The• Low-Power Alternativefor the MC100EP16 receiver accepts low-voltage differential signaling
(LVDS), positive-emitter-coupled logic (PECL), or• Low 100-ps (Maximum) Part-to-Part Skew current-mode logic (CML) input signalsat rates upto• 25 mVof Receiver Input Threshold Hysteresis 2 Gbps and repeatsit as either an LVDSor PECLOver 0-Vto 4-V Input Voltage Range output signal. The signal path through the deviceis• Inputs Electrically Compatible With
CML, and LVDS Signal Levels 3.3-V Supply Operation• LVDT Integrates 110-Ω Terminating• Offeredin SOIC and MSOP
2 Applications• Wireless Infrastructure• Telecom Infrastructure• Printers
