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SN65EPT22DRTIN/a4263avai3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Buffer 8-SOIC -40 to 85


SN65EPT22DR ,3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Buffer 8-SOIC -40 to 85Features 3 DescriptionThe SN65EPT22 is a low power dual LVTTL to1• Dual 3.3V LVTTL to LVPECL Buffer ..
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SN65EPT22DR
3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Buffer
Sample & Support & Product Tools & Technical Community Buy Folder Documents Software SN65EPT22 SLLS926B – DECEMBER 2008 – REVISED NOVEMBER 2014 SN65EPT22 3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Buffer 1 Features 3 Description The SN65EPT22 is a low power dual LVTTL to 1• Dual 3.3V LVTTL to LVPECL Buffer LVPECL translator device. The device includes • Operating Range circuitry to maintain known logic HIGH level when – LVPECL V = 3.0 V to 3.6 V With inputs are in open condition. The SN65EPT22 is CC housed in an industry standard SOIC-8 package and GND = 0 V is also available in TSSOP-8 package option. • Support for Clock Frequencies to 2.0 GHz (typ) • 420 ps Typical Propagation Delay (1) Device Information • Deterministic HIGH Output Value for Open Input PART NUMBER PACKAGE BODY SIZE (NOM) Conditions SOIC (8) 4.90mm x 3.91mm SN65EPT22 • Built-in Temperature Compensation VSSOP (8) 3.00mm x 3.00mm • Drop in Compatible to MC100ELT23 (1) For all available packages, see the orderable addendum at the end of the datasheet. • PNP Single Ended Inputs for Minimal Loading 2 Applications • Data and Clock Transmission Over Backplane • Signaling Level Conversion 4 Simplified Schematic V = V - 2 V TERM CC Transmission Line R ~ Z ~ t O Z O SN65EPT22 LVPECL Transmission Line ~ R Z ~ t O Z O V = V - 2 V TERM CC 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
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