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74LS92-SN54LS90J-SN54LS92J-SN74LS92N Fast Delivery,Good Price
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74LS92N/a2avaiDivide-by-Twelve Counters
74LS92PanasonicN/a566avaiDivide-by-Twelve Counters
SN74LS92NTEXASN/a24avaiDECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER
SN54LS90JN/a10avaiDECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER
SN54LS92JTI?N/a20avaiDECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER


74LS92 ,Divide-by-Twelve CountersLOGIC DIAGRAM CONNECTION DIAGRAMDIP (TOP VIEW)LS931 14CP CP1 0J Q J Q J Q J Q2 13NC14 MR1CP0CP CP C ..
74LS92 ,Divide-by-Twelve CountersLOGIC DIAGRAM CONNECTION DIAGRAMDIP (TOP VIEW)LS906MS1 1 14CP CP1 0MS272 13NCMR1S S S SD D D DJ Q J ..
74LS92 ,Divide-by-Twelve CountersLOGIC DIAGRAM CONNECTION DIAGRAMDIP (TOP VIEW)LS931 14CP CP1 0J Q J Q J Q J Q2 13NC14 MR1CP0 CP CP ..
74LS93 ,4-bit Binary Counters
74LS95 ,4-bit Parallel Access Shift RegistersSN54/74LS95B4-BIT SHIFT REGISTERThe SN54/74LS95B is a 4-Bit Shift Register with serial and parallel ..
74LS95B , 4-BIT RIGHT/LEFT SHIGT REGISTER
7MBI40N-120 ,IGBT(1200V/40A)IGBT MODULE ( N series )n n n n Outline Drawing• • • • • • Overcurrent Limiting Function( 4 ~ 5 Tim ..
7MBP100RA060 ,Intelligent Power Module
7MBP100RA120 ,IGBT-IPM(1200V/100A)
7MBP150RA060 ,Intelligent Power Module
7MBP150RA120 ,IGBT-IPM(1200V/150A)
7MBP25RA120 ,IGBT-IPM(1200V/25A)


74LS92-SN54LS90J-SN54LS92J-SN74LS92N
DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER
DECADE COUNTER;
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER

The SN54/ 74LS90, SN54/74LS92 and SN54/74LS93 are high-speed
4-bit ripple type counters partitioned into two sections. Each counter has a di-
vide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or
divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transi-
tion on the clock inputs. Each section can be used separately or tied together
(Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of
the counters have a 2-input gated Master Reset (Clear), and the LS90 also
has a 2-input gated Master Set (Preset 9). Low Power Consumption ...Typically 45 mW High Count Rates ...Typically 42 MHz Choice of Counting Modes... BCD, Bi-Quinary, Divide-by-Twelve,
Binary Input Clamp Diodes Limit High Speed Termination Effects
PIN NAMES LOADING (Note a)

CP0 Clock (Active LOW going edge) Input to
÷2 Section
CP1 Clock (Active LOW going edge) Input to
÷5 Section (LS90), ÷6 Section (LS92)
CP1 Clock (Active LOW going edge) Input to
÷8 Section (LS93)
MR1, MR2 Master Reset (Clear) Inputs
MS1, MS2 Master Set (Preset-9, LS90) Inputs Output from ÷2 Section (Notes b & c)
Q1, Q2, Q3 Outputs from ÷5 (LS90), ÷6 (LS92),
÷8 (LS93) Sections (Note b)
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74)
b. Temperature Ranges.
c. The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 input of the device.
d. To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns.
LOGIC SYMBOL

VCC = PIN 5
VCC = PIN 5
VCC = PIN 5
LS90 LS92 LS93
9811 67 98119811
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