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Partno Mfg Dc Qty AvailableDescript
SN74LS76NTIN/a200avaiDUAL JK FLIP-FLOP WITH SET AND CLEAR
SN54LS76JTIN/a100avaiDUAL JK FLIP-FLOP WITH SET AND CLEAR


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SN54LS76J-SN74LS76N
DUAL JK FLIP-FLOP WITH SET AND CLEAR
DUAL JK FLIP-FLOP
WITH SET AND CLEAR

The SN54/74LS76A offers individual J, K, Clock Pulse, Direct Set and Di-
rect Clear inputs. These dual flip-flops are designed so that when the clock
goes HIGH, the inputs are enabled and data will be accepted. The Logic Level
of the J and K inputs will perform according to the Truth Table as long as mini-
mum set-up times are observed. Input data is transferred to the outputs on the
HIGH-to-LOW clock transitions.
MODE SELECT — TRUTH TABLE

*Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable
if SD and CD go HIGH simultaneously.
H,h = HIGH Voltage Level
L,l = LOW Voltage Level
X = Immaterial
l, h (q) = Lower case letters indicate the state of the referenced input (or output) one setup time prior
to the HIGH-to-LOW clock transition
LOGIC DIAGRAM

CLEAR (CD)
CLOCK (CP)
SET (SD)
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