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JM38510/32503BRA |JM3851032503BRATIN/a56avaiOctal D-Type Edge Triggered Flip-Flops with 3-State Outputs
SNJ54LS374FKTIN/a11avaiOctal D-Type Edge Triggered Flip-Flops with 3-State Outputs
SNJ54LS374JTI ?N/a20avaiOctal D-Type Edge Triggered Flip-Flops with 3-State Outputs
SN54LS374JTI?N/a300avaiOCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT
SN54LS374J. |SN54LS374JTIN/a500avaiOCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT


SN54LS374J. ,OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT/sc/package.2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265SN54LS373, SN54LS374, SN54S373, SN54S374, ..
SN54LS377J ,OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLEfeatures the common Enablerather then common Master Reset.J SUFFIX• 8-Bit High Speed Parallel Regis ..
SN54LS378J ,OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE
SN54LS378J ,OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE
SN54LS379J ,OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLESN54/74LS377SN54/74LS378OCTAL D FLIP-FLOP WITH ENABLE;SN54/74LS379HEX D FLIP-FLOP WITH ENABLE;4-BIT ..
SN54LS390J ,DUAL DECADE COUNTER; DUAL 4-STAGE BINARY COUNTERFUNCTIONAL DESCRIPTIONEach half of the SN54/ 74LS393 operates in the Modulo 16 section operates in ..
SN74HC125 ,Quadruple Bus Buffer Gates With 3-State OutputsSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareSN54HC125SN74HC125SC ..
SN74HC125D ,Quadruple Bus Buffer Gates With 3-State OutputsMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITV S ..
SN74HC125DBR ,Quadruple Bus Buffer Gates With 3-State Outputs SCLS104E–AUGUST 1984–REVISED DECEMBER 20155 Pin Configuration and FunctionsD, DB, N, NS, J, or PW ..
SN74HC125DR ,Quadruple Bus Buffer Gates With 3-State OutputsMaximum Ratings.. 49 Application and Implementation...... 116.2 ESD Ratings ...... 49.1 Application ..
SN74HC125N ,Quadruple Bus Buffer Gates With 3-State OutputsFeatures... 17 Parameter Measurement Information 92 Applications..... 18 Detailed Description...... ..
SN74HC125NSR ,Quadruple Bus Buffer Gates With 3-State OutputsLogic Diagram (Positive Logic)1 101OE 3OE2 3 9 81A 1Y 3A 3Y4 132OE 4OE5 6 12 112A 2Y 4A 4YPin numbe ..


JM38510/32503BRA-SN54LS374J-SN54LS374J.-SNJ54LS374FK-SNJ54LS374J
Octal D-Type Edge Triggered Flip-Flops with 3-State Outputs
Buffered Control Inputs Clock-Enable Input Has Hysteresis toImprove Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data
Lines (’S373 and ’S374)
description

These 8-bit registers feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The
high-impedance 3-state and increased
high-logic-level drive provide these registers with
the capability of being connected directly to and
driving the bus lines in a bus-organized system
without need for interface or pullup components.
These devices are particularly attractive for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The eight latches of the ’LS373 and ’S373 are
transparent D-type latches, meaning that while
the enable (C or CLK) input is high, the Q outputs
follow the data (D) inputs. When C or CLK is taken
low, the output is latched at the level of the data
that was set up.
The eight flip-flops of the ’LS374 and ’S374 are
edge-triggered D-type flip-flops. On the positive
transition of the clock, the Q outputs are set to the
logic states that were set up at the D inputs.
Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design
as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered
output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic
levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly.
OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new
data can be entered, even while the outputs are off.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LS373, SN54LS374, SN54S373,
SN54S374 . . . FK PACKAGE
(TOP VIEW)
1QOC
GND
GND
VCC† C for ’LS373 and ’S373; CLK for ’LS374 and ’S374. C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.
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