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Partno Mfg Dc Qty AvailableDescript
SN74LS368NTIN/a111avai3-STATE HEX BUFFERS
SN54LS365JTIN/a50avai3-STATE HEX BUFFERS
SN54LS366JTIN/a4800avai3-STATE HEX BUFFERS
SN54LS367JTIN/a50avai3-STATE HEX BUFFERS
SN54LS368JTIN/a300avai3-STATE HEX BUFFERS
SN74LS367NN/a40avai3-STATE HEX BUFFERS


SN54LS366J ,3-STATE HEX BUFFERSSN54/74LS365ASN54/74LS366ASN54/74LS367A3-STATE HEX BUFFERSSN54/74LS368AThese devices are high speed ..
SN54LS367AJ ,3-state hex bufferlogic diagrams (positive logic)'365A. 'Ls365A '366A. 'Ls366A '367A, 'LS367A '368A, 'LS368AG1 (1) G1 ..
SN54LS367J ,3-STATE HEX BUFFERSSN54/74LS365ASN54/74LS366ASN54/74LS367A3-STATE HEX BUFFERSSN54/74LS368AThese devices are high speed ..
SN54LS368AJ ,3-state hex bufferSN54/74LS365ASN54/74LS366ASN54/74LS367A3-STATE HEX BUFFERSSN54/74LS368AThese devices are high speed ..
SN54LS368J ,3-STATE HEX BUFFERSSN54/74LS365ASN54/74LS366ASN54/74LS367A3-STATE HEX BUFFERSSN54/74LS368AThese devices are high speed ..
SN54LS37 ,QUAD 2-INPUT NAND BUFFER
SN74HC112N ,Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Presetmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HC11D ,Triple 3-Input Positive-AND Gateslogic diagram (positive logic)AYBC†absolute
SN74HC11D ,Triple 3-Input Positive-AND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HC11DR ,Triple 3-Input Positive-AND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HC11N ,Triple 3-Input Positive-AND Gatesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74HC11NSR ,Triple 3-Input Positive-AND Gates/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..


SN54LS365J-SN54LS366J-SN54LS367J-SN54LS368J-SN74LS367N-SN74LS368N
Hex 3-STATE Buffer/Bus Driver
3-STATE HEX BUFFERS
These devices are high speed hex buffers with 3-state outputs. They are
organized as single 6-bit or 2-bit/4-bit, with inverting or non-inverting data (D)
paths. The outputs are designed to drive 15 TTL Unit Loads or 60 Low Power
Schottky loads when the Enable (E) is LOW.
When the Output Enable (E) is HIGH, the outputs are forced to a high
impedance “off” state. If the outputs of the 3-state devices are tied together,
all but one device must be in the high impedance state to avoid high currents
that would exceed the maximum ratings. Designers should ensure that Output
Enable signals to 3-state devices whose outputs are tied together are
designed so there is no overlap.
GUARANTEED OPERATING RANGES
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