74LS293 ,4-bit Binary CountersSN54/74LS290SN54/74LS293DECADE COUNTER;4-BIT BINARY COUNTERThe SN54/74LS290 and SN54/74LS293 are hi ..
74LS293 ,4-bit Binary CountersLOGIC DIAGRAMSLS290 ** ** * * * * * * ** ** ** * * * * * ** * * ** * * * * * * * * * * * * * * ..
74LS293 ,4-bit Binary CountersSN54/74LS290SN54/74LS293DECADE COUNTER;4-BIT BINARY COUNTERThe SN54/74LS290 and SN54/74LS293 are hi ..
74LS295 , 4-BIT RIGHT-SHIFT LEFT-SHIFT REGISTERS WITH 3-STATE OUTPUTS
74LS30 ,8-Input NAND GateGeneral DescriptionThis device contains a single gate which performs the logicNAND function. Orderi ..
74LS32 ,Quad 2-Input OR GateGeneral DescriptionThis device contains four independent gates each of whichperforms the logic OR f ..
79L05ACZ , Three-Terminal Low Current Negative Voltage Regulators
79L06 , TO-92 Plastic-Encapsulate Transistors
79L06 , TO-92 Plastic-Encapsulate Transistors
79L06 , TO-92 Plastic-Encapsulate Transistors
79L06 , TO-92 Plastic-Encapsulate Transistors
79L06 , TO-92 Plastic-Encapsulate Transistors
74LS293-SN54LS290J
4-bit Binary Counters
DECADE COUNTER;
4-BIT BINARY COUNTERThe SN54/74LS290 and SN54/74LS293 are high-speed 4-bit ripple type
counters partitioned into two sections. Each counter has a divide-by-two sec-
tion and either a divide-by-five (LS290) or divide-by-eight (LS293) section
which are triggered by a HIGH-to-LOW transition on the clock inputs. Each
section can be used separately or tied together (Q to CP)to form BCD,
Bi-quinary, or Modulo-16 counters. Both of the counters have a 2-input gated
Master Reset (Clear), and the LS290 also has a 2-input gated Master Set
(Preset 9). Corner Power Pin Versions of the LS90 and LS93 Low Power Consumption . . . Typically 45 mW High Count Rates . . . Typically 42 MHz Choice of Counting Modes . . . BCD, Bi-Quinary, Binary Input Clamp Diodes Limit High Speed Termination Effects- --- --- -- ----- - -- --
CONNECTION DIAGRAM DIP (TOP VIEW)NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.- --- --- -- ---- - - -- --
PIN NAMES LOADING (Note a)CP0 Clock (Active LOW going edge) Input to ÷2 Section.
CP1 Clock (Active LOW going edge) Input to ÷5 Section (LS290).
CP1 Clock (Active LOW going edge) Input to ÷8 Section (LS293).
MR1, MR2 Master Reset (Clear) Inputs
MS1, MS2 Master Set (Preset-9, LS290) Inputs Output from ÷2 Section (Notes b & c)
Q1, Q2, Q3 Outputs from ÷5 & ÷8 Sections (Note b)
NOTES:
