SN54LS165AJ ,Parallel-Load 8-Bit Shift RegistersSN54165, SN54LS165A, SN74165, SN74LS165A PARALLEL-LOAD 8-BIT SHIFT REGISTERSThe SN54165 and SN74165 ..
SN54LS165J ,8-BIT PARALLEL-TO-SERIAL SHIFT REGISTERSN54/74LS160ASN54/74LS161ASN54/74LS162ABCD DECADE COUNTERS/SN54/74LS163A4-BIT BINARY COUNTERSThe LS ..
SN54LS166AJ ,Parallel-Load 8-Bit Shift Registers
SN54LS166J ,8-BIT SHIFT REGISTERS
SN54LS166J ,8-BIT SHIFT REGISTERS
SN54LS166J ,8-BIT SHIFT REGISTERS
SN74HC00D ,Quad 2-Input Positive-NAND GatesElectrical Characteristics....... 512.3 Receiving Notification of Documentation Updates 116.6 Switc ..
SN74HC00DBR ,Quad 2-Input Positive-NAND Gates 14-SSOP -40 to 85Logic Diagram (Positive Logic)• Power: Telecom or Server AC/DC SupplyA(Single Controller: Analog an ..
SN74HC00DG4 ,Quad 2-Input Positive-NAND Gates 14-SOIC -40 to 85Electrical Characteristics....... 512.3 Receiving Notification of Documentation Updates 116.6 Switc ..
SN74HC00DR ,Quad 2-Input Positive-NAND GatesMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNITSup ..
SN74HC00DRG4 ,Quad 2-Input Positive-NAND Gates 14-SOIC -40 to 85Maximum Ratings.. 411.2 Layout Example ...... 106.2 ESD Ratings........ 412 Device and Documentatio ..
SN74HC00N ,Quad 2-Input Positive-NAND GatesLogic Diagram (Positive Logic)• Power: Telecom or Server AC/DC SupplyA(Single Controller: Analog an ..
JM38510/30608BEA-SN54LS165AJ-SNJ54LS165AJ-SNJ54LS165AW
Parallel-Load 8-Bit Shift Registers
TYPE TYPICAL MAXIMUM
CLOCK FREQUENCY
TYPICAL
POWER DISSIPATION’165 26 MHz 210 mW
’LS165A 35 MHz 90 mW
descriptionThe ’165 and ’LS165A are 8-bit serial shift
registers that shift the data in the direction of QAtoward QH when clocked. Parallel-in access to
each stage is made available by eight individual,
direct data inputs that are enabled by a low level
at the shift/load (SH/LD) input. These registers
also feature gated clock (CLK) inputs and
complementary outputs from the eighth bit. All
inputs are diode-clamped to minimize
transmission-line effects, thereby simplifying
system design.
Clocking is accomplished through a two-input
positive-NOR gate, permitting one input to be
used as a clock-inhibit function. Holding either of
the clock inputs high inhibits clocking, and holding
either clock input low with SH/LD high enables the
other clock input. Clock inhibit (CLK INH) should
be changed to the high level only while CLK is
high. Parallel loading is inhibited as long as SH/LD
is high. Data at the parallel inputs are loaded
directly into the register while SH/LD is low,
independently of the levels of CLK, CLK INH, or
serial (SER) inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LS165A... FK PACKAGE
(TOP VIEW)CLKSH/LDNC
SER
CLK INH
GND
CLKH
GND
CLK INH
SER
NC – No internal connection
