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SN54LS109JTIN/a700avaiDUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP


SN54LS109J ,DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
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SN54LS109J
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
DUAL JK POSITIVE
EDGE-TRIGGERED FLIP-FLOP

The SN54/74LS109A consists of two high speed completely independent
transition clocked JK flip-flops. The clocking operation is independent of rise
and fall times of the clock waveform. The JK design allows operation as a D
flip-flop by simply connecting the J and K pins together.
LOGIC DIAGRAM
- --- ------
MODE SELECT — TRUTH TABLE
Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the LOW to HIGH clock transition.
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