SN54HC139J ,Dual 2-Line To 4-Line Decoders/Demultiplexerslogic diagram (positive logic)41Y011G 51Y161Y221A73 1Y31B122Y0152G 112Y1102Y2142A92Y3132BPin number ..
SN54HC148J ,8-Line To 3-Line Priority Encodersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN54HC14J ,Hex Schmitt-trigger InvertersFeatures list 1• Added Pin Configuration and Functions section, ESD Ratings table, Feature Descript ..
SN54HC151J ,8-Line To 1-Line Data Selectors/Multiplexersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN54HC153J ,Dual 4-Line To 1-Line Data Selectors/Multiplexers SCLS112D − DECEMBER 1982 − REVISED ..
SN54HC157J ,Quadruple 2-Line To 1-Line Data Selectors/Multiplexersmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74F244DB ,OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SDFS063A − D2932, MARCH 1987 − REVISED OC ..
SN74F244DB ,OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTSmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74F244DBR ,Octal Buffers/Drivers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74F244DBR ,Octal Buffers/Drivers With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only andfunctio ..
SN74F244DBRG4 , OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74F244DW ,Octal Buffers/Drivers With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only andfunctio ..
JM38510/65803BEA-SN54HC139J-SNJ54HC139FK-SNJ54HC139J
Dual 2-Line To 4-Line Decoders/Demultiplexers
Low Power Consumption, 80-µA Max ICC Typical tpd = 10 ns ±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max Incorporate Two Enable Inputs to SimplifyCascading and/or Data Reception
description/ordering informationThe ’HC139 devices are designed for
high-performance memory-decoding or
data-routing applications requiring very short
propagation delay times. In high-performance
memory systems, these decoders can minimize
the effects of system decoding. When employed
with high-speed memories utilizing a fast enable
circuit, the delay time of these decoders and the
enable time of the memory usually are less than
the typical access time of the memory. This means
that the effective system delay introduced by the
decoders is negligible.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
2Y0
2Y1
1Y0
1Y1
1Y21GNC
2Y32Y22G
1Y3
GND
SN54HC139... FK PACKAGE
(TOP VIEW)NC − No internal connection
1Y0
1Y1
1Y2
1Y3
GND
2Y0
2Y1
2Y2
2Y3
