SN5414J ,Hex Schmitt-trigger InvertersBlock Diagram... 134 Revision HistoryChanges from Revision B (February 2002) to Revision C Page• Ad ..
SN54153J ,Dual 4-Line To 1-Line Data Selectors/Multiplexers
SN54153J ,Dual 4-Line To 1-Line Data Selectors/Multiplexers
SN54154J ,4-Line To 16-Line Decoders/Demultiplexers
SN54156J , DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SN54160J , SYNCHRONOUS 4-BIT COUNTERS
SN74CBT3245APWRG4 ,Octal FET Bus Switch 20-TSSOP -40 to 85logic diagram (positive logic)2 18A1 B19 11A8 B819OEPin numbers shown are for the DB, DBQ, DGV, DW, ..
SN74CBT3245ARGYR ,Octal FET Bus Switchlogic diagram (positive logic)2 18A1 B19 11A8 B819OEPin numbers shown are for the DB, DBQ, DGV, DW, ..
SN74CBT3245CDBQR ,Octal FET Bus Switch With -2 V Undershoot Protectionmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74CBT3245CDGVR ,Octal FET Bus Switch With -2 V Undershoot Protectionmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74CBT3245CDWR ,Octal FET Bus Switch With -2 V Undershoot Protection SCDS131A − SEPTEMBER 2003 ..
SN74CBT3245CPWR ,Octal FET Bus Switch With -2 V Undershoot Protection/sc/package.FUNCTION TABLEINPUT INPUT INPUT/OUTPUT INPUT/OUTPUTFUNCTION FUNCTIONOE AL B A port = B ..
SN5414J-SNJ5414J
Hex Schmitt-trigger Inverters
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SN5414, SN54LS14, SN7414, SN74LS14SDLS049C–DECEMBER 1983–REVISED NOVEMBER 2016
SNx414 and SNx4LS14 Hex Schmitt-Trigger Inverters Features Operation From Very Slow Edges Improved Line-Receiving Characteristics High Noise Immunity
Applications HVAC Gateways Residential Ductless Air Conditioning Outdoor
Units Robotic Controls Industrial Stepper Motors Power Meter and Power Analyzers Digital Input Modules for Factory Automation
DescriptionEach circuitin SNx414 and SNx4LS14 functions as inverter. However, becauseof the Schmitt-Trigger
action, they have different input threshold levels for
positive-going (VT+) and negative-going (VT–) signals.
These circuits are temperature compensated and can triggered from the slowestof input ramps and still
give clean, jitter-free output signals.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Logic Diagram (Positive Logic)
