SMP08FP-SMP08FS Fast Delivery |IC PHOENIX CO.,LIMITED

SMP08FS ,Octal Sample-and-Hold with Multiplexed InputSpecifications subject to change without notice.–2–REV. DSMP08ABSOLUTE MAXIMUM RATINGSORDERING GUID ..
SMP08FS ,Octal Sample-and-Hold with Multiplexed Inputapplications including amplifier offset or VCA gainadjustments. One or more SMP08s can be used with ..
SMP08FS ,Octal Sample-and-Hold with Multiplexed InputCHARACTERISTICSLogic Input High Voltage V 2.4 VINHLogic Input Low Voltage V 0.8 VINLLogic Input Cur ..
SMP100-120 ,COMMUNICATION EQUIPMENT PROTECTION: TRISIL TMSMP100-xxxTMCOMMUNICATION EQUIPMENT PROTECTION: TRISIL
SMP100-140 ,COMMUNICATION EQUIPMENT PROTECTION: TRISIL TMSMP100-xxxTMCOMMUNICATION EQUIPMENT PROTECTION: TRISIL
SMP100-140H225 ,TRISILFEATURESBIDIRECTIONALCROWBAR PROTECTIONVOLTAGE RANGE : FROM 8V to 270VREPETITIVEPEAK PULSE CURRENT: ..
SN74ALS575ADW ,Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE ..
SN74ALS576BDW ,Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ALS576BN ,Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs ..
SN74ALS576BNSR ,Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V ..
SN74ALS580BN ,Octal D-Type Transparent Latches With 3-State Outputs SDAS277 − JA ..
SN74ALS620A ,Octal Bus Transceivers SN74ALS620A, SN74ALS621A, SN74ALS623A, SN74AS623 OCTAL BUS TRANSCEIVERS SDAS226A – DECEMBER 1982 ..

SMP08FP-SMP08FS
Octal Sample-and-Hold with Multiplexed Input
REV.DOctal Sample-and-Hold
with Multiplexed Input
FUNCTIONAL BLOCK DIAGRAM
DGND
VDD
CH0OUT
CH1OUT
CH2OUT
CH3OUT
CH4OUT
CH5OUT
CH6OUT
CH7OUT
VSS
INPUT
(LSB)B
(MSB)INH
FEATURES
Internal Hold Capacitors
Low Droop Rate
TTL/CMOS Compatible Logic Inputs
Single or Dual Supply Operation
Break-Before-Make Channel Addressing
Compatible With CD4051 Pinout
Low Cost
APPLICATIONS
Multiple Path Timing Deskew for ATE
Memory Programmers
Mass Flow/Process Control Systems
Multichannel Data Acquisition Systems
Robotics and Control Systems
Medical and Analytical Instrumentation
Event Analysis
Stage Lighting Control
GENERAL DESCRIPTION
The SMP08 is a monolithic octal sample-and-hold; it has eight
internal buffer amplifiers, input multiplexer, and internal hold
capacitors. It is manufactured in an advanced oxide isolated
CMOS technology to obtain high accuracy, low droop rate, and
fast acquisition time. The SMP08 has a typical linearity error of
only 0.01% and can accurately acquire a 10-bit input signal to
±1/2 LSB in less than 7 microseconds. The SMP08’s output
swing includes the negative supply in both single and dual sup-
ply operation.
The SMP08 was specifically designed for systems that use a
calibration cycle to adjust a multiple of system parameters. The
low cost and high level of integration make the SMP08 ideal for
calibration requirements that have previously required an
ASIC, or high cost multiple D/A converters.
*. Patent No. 4,739,281.
The SMP08 is also ideally suited for a wide variety of sample-
and-hold applications including amplifier offset or VCA gain
adjustments. One or more SMP08s can be used with single or
multiple DACs to provide multiple set points within a system.
The SMP08 offers significant cost and size reduction over dis-
crete designs. It is available in a 16-pin plastic DIP, or surface-
mount SOIC package.
SMP08–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
NOTES
(@ VDD = +5 V, VSS = –5 V, DGND = 0 V, RL = No Load, TA = –408C to +858C for SMP08F,
unless otherwise noted)
(@ VDD = +12 V, VSS = 0 V, DGND = 0 V, RL = No Load, TA = –408C to +858C for SMP08F,
unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, 17 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, 17 V
VLOGIC to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD
VIN to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VSS, VDD
VOUT to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VSS, VDD
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . .±20 mA
(Not Short-Circuit Protected)
Operating Temperature Range
FP, FS . . . . . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . .+300°C
*θJA is specified for worst case mounting conditions, i.e., θJA is specified for device
in socket for plastic DIP package; θJA is specified for device soldered to printed
circuit board for SO package.
ORDERING GUIDE
PIN CONNECTIONS
CH4OUT
CH0OUT
CH1OUT
CH2OUT
VDD
CH6OUT
INPUT
CH7OUT
B CONTROL
A CONTROL
CH3OUTCH5OUT
INH
VSS
DGNDC CONTROL
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SMP08 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Figure 3.Droop Rate vs. Input Voltage
Figure 6.Slew Rate vs. VDD
Figure 9.Offset Voltage vs. Input
Voltage
INPUT VOLTAGE – Volts
DROOP RATE – mV/s1023456789
Figure 2.Droop Rate vs. Input Voltage
TEMPERATURE – °C
HOLD STEP – mV–55–3585–155254565
Figure 5.Hold Step vs. Temperature
INPUT VOLTAGE – Volts
OFFSET VOLTAGE – mV
–10
Figure 8.Offset Voltage vs. Input
Voltage
SMP08–Typical Performance Characteristics
TEMPERATURE – °C
DROOP RATE – mV/s
–55–35125–15525658510545
Figure 1.Droop Rate vs. Temperature
INPUT VOLTAGE – Volts
HOLD STEP – mV1023456789
Figure 4.Hold Step vs. Input Voltage
INPUT VOLTAGE – Volts
OFFSET VOLTAGE – mV
–101023456789
Figure 7.Offset Voltage vs. Input
Voltage
TEMPERATURE – °C
OFFSET VOLTAGE – mV
–55–35125–15525658510545
Figure 10. Offset Voltage vs.
Temperature
VDD – Volts
SUPPLY CURRENT – mA18810121416
Figure 11.Supply Current vs. VDD
Figure 12.Sample Mode Power
Supply Rejection
FREQUENCY – Hz
GAIN – dB
1001k10M10k100k1M
PHASE SHIFT – Degrees
Figure 13.Gain, Phase Shift vs.
Frequency
FREQUENCY – Hz
PEAK-TO-PEAK OUTPUT – Volts
10k100k10M1M
Figure 15.Maximum Output Voltage
vs. Frequency
Figure 14.Output Impedance vs.
Frequency
FREQUENCY – Hz
REJECTION RATIO – dB
–101001M1k10k100k
Figure 16.Hold Mode Power Supply
Rejection
SMP08
VCC
+15V
Figure 17.Burn-In Circuit
OUTPUT BUFFERS (Pins 1, 2, 4, 5, 12, 13, 14, 15)
The buffer offset specification is 10 mV; this is less than 1/2 LSB
of an 8-bit DAC with 10 V full scale. The hold step (magni-
tude of step caused in the output voltage when switching from
sample-to-hold mode, also referred to as the pedestal error or
sample-to-hold offset), is about 2.5 mV with little variation
over the full output voltage range, TA = +25°C to +85°C. The
droop rate of a held channel is 2 mV/s typical and 20 mV/s
maximum.
The buffers are designed to drive loads connected to ground.
The outputs can source more than 20 mA, over the full voltage
range, but have limited current sinking capability near VSS. In
split supply operation, symmetrical output swings can be ob-
tained by restricting the output range to 2 V from either supply.
On-chip SMP08 buffers eliminate potential stability problems
associated with external buffers; outputs are stable with ca-
pacitive loads up to 500 pF. However, since the SMP08’s
buffer outputs are not short-circuit protected, care should be
taken to avoid shorting any output to the supplies or ground.
SIGNAL INPUT (Pin 3)
The signal input should be driven from a low impedance volt-
age source such as the output of an op amp. The op amp
should have a high slew rate and fast settling time if the
SMP08’s acquisition time characteristics are to be maintained.
As with all CMOS devices, all input voltages should be kept
within range of the supply rails (VSS < VIN < VDD) to avoid the
possibility of latchup. If single supply operation is desired, op
amps such as the OP183 or AD820 that have input and output
voltage compliances including ground, can be used to drive the
inputs. Split supplies, such as ±7.5 V, can be used with the
SMP08.
APPLICATION TIPS
All unused digital inputs should be connected to logic LOW
and unused analog inputs connected to analog ground. For
APPLICATIONS INFORMATION
The SMP08, a multiplexed octal S/H, minimizes board space in
systems requiring cycled calibration or an array of control volt-
ages. When used in conjunction with a low cost 16-bit D/A, the
SMP08 can easily be integrated into microprocessor based sys-
tems. Since the SMP08 features break-before-make switching
and an internal decoder, no external logic is required. The
SMP08 has an internally regulated TTL supply so that TTL/
CMOS compatibility is maintained over the full supply range.
See Figure 18 for channel decode address information.
POWER SUPPLIES
The SMP08 is capable of operating with either single or dual
supplies, over a voltage range of 7 volts to 15 volts. Based on the
supply voltages chosen, VDD and VSS establish the input and
output voltage range, which is:
(VSS +0.06 V) ≤ VOUT/IN ≤ (VDD –2 V)
Note that several specifications, including acquisition time, off-
set and output voltage compliance, will degrade for supply volt-
ages of less than 7 V.
If split supplies are used, the negative supply should be bypassed
with a 0.1 μF capacitor in parallel with a 10 μF to ground. The
internal hold capacitors are connected to this supply pin and any
noise will appear at the outputs.
In single supply applications, it is extremely important that the
VSS (negative supply) pin is connected to a clean ground. The
hold capacitors are internally tied to the VSS (negative) rail. Any
ground noise or disturbance will directly couple to the output of
the sample-and-hold, degrading the signal-to-noise perfor-
mance. The analog and digital ground traces on the circuit
board should be physically separated to reduce digital switching
noise from entering the analog circuitry.
POWER SUPPLY SEQUENCING
VDD should be applied to the SMP08 before the logic input sig-

Partno	Mfg	Dc	Qty	Available	Descript
SMP08FP	AD	N/a	7	avai	Octal Sample-and-Hold with Multiplexed Input
SMP08FS	AD ?	N/a	94	avai	Octal Sample-and-Hold with Multiplexed Input
SMP08FS	AD	N/a	1000	avai	Octal Sample-and-Hold with Multiplexed Input
SMP08FS	PMI	N/a	68	avai	Octal Sample-and-Hold with Multiplexed Input